2022-12-04 11:03:45 +00:00
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// SPDX-FileCopyrightText: 2019-2022 Connor McLaughlin <stenzek@gmail.com> and contributors.
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// SPDX-License-Identifier: (GPL-3.0 OR CC-BY-NC-ND-4.0)
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2021-01-21 07:59:40 +00:00
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#include "multitap.h"
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#include "common/log.h"
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#include "common/types.h"
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#include "controller.h"
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#include "memory_card.h"
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#include "pad.h"
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2022-07-08 12:43:38 +00:00
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#include "util/state_wrapper.h"
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2021-01-21 07:59:40 +00:00
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Log_SetChannel(Multitap);
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2021-03-01 22:59:59 +00:00
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Multitap::Multitap()
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2021-01-21 07:59:40 +00:00
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{
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Reset();
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}
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void Multitap::Reset()
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{
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m_transfer_state = TransferState::Idle;
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m_selected_slot = 0;
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m_controller_transfer_step = 0;
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m_transfer_all_controllers = false;
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m_invalid_transfer_all_command = false;
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m_current_controller_done = false;
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m_transfer_buffer.fill(0xFF);
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}
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2021-03-01 22:59:59 +00:00
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void Multitap::SetEnable(bool enable, u32 base_index)
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{
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if (m_enabled != enable || m_base_index != base_index)
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{
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m_enabled = enable;
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m_base_index = base_index;
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Reset();
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}
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}
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2021-01-21 07:59:40 +00:00
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bool Multitap::DoState(StateWrapper& sw)
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{
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sw.Do(&m_transfer_state);
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sw.Do(&m_selected_slot);
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sw.Do(&m_controller_transfer_step);
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sw.Do(&m_invalid_transfer_all_command);
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sw.Do(&m_transfer_all_controllers);
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sw.Do(&m_current_controller_done);
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sw.Do(&m_transfer_buffer);
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return !sw.HasError();
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}
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void Multitap::ResetTransferState()
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{
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m_transfer_state = TransferState::Idle;
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m_selected_slot = 0;
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m_controller_transfer_step = 0;
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m_current_controller_done = false;
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// Don't reset m_transfer_all_controllers here, since it's queued up for the next transfer sequence
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// Controller and memory card transfer resets are handled in the Pad class
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}
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bool Multitap::TransferController(u32 slot, const u8 data_in, u8* data_out) const
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{
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2023-01-11 09:10:21 +00:00
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Controller* const selected_controller = Pad::GetController(m_base_index + slot);
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2021-01-21 07:59:40 +00:00
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if (!selected_controller)
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{
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*data_out = 0xFF;
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return false;
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}
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return selected_controller->Transfer(data_in, data_out);
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}
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bool Multitap::TransferMemoryCard(u32 slot, const u8 data_in, u8* data_out) const
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{
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2023-01-11 09:10:21 +00:00
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MemoryCard* const selected_memcard = Pad::GetMemoryCard(m_base_index + slot);
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2021-01-21 07:59:40 +00:00
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if (!selected_memcard)
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{
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*data_out = 0xFF;
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return false;
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}
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return selected_memcard->Transfer(data_in, data_out);
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}
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bool Multitap::Transfer(const u8 data_in, u8* data_out)
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{
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bool ack = false;
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switch (m_transfer_state)
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{
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case TransferState::Idle:
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{
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switch (data_in)
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{
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case 0x81:
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case 0x82:
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case 0x83:
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case 0x84:
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{
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m_selected_slot = (data_in & 0x0F) - 1u;
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ack = TransferMemoryCard(m_selected_slot, 0x81, data_out);
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if (ack)
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m_transfer_state = TransferState::MemoryCard;
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}
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break;
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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{
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m_selected_slot = data_in - 1u;
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ack = TransferController(m_selected_slot, 0x01, data_out);
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if (ack)
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{
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m_transfer_state = TransferState::ControllerCommand;
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if (m_transfer_all_controllers)
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{
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// Send access byte to remaining controllers for this transfer mode
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u8 dummy_value;
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for (u32 i = 0; i < 4; i++)
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{
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if (i != m_selected_slot)
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TransferController(i, 0x01, &dummy_value);
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}
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}
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}
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}
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break;
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default:
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{
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*data_out = 0xFF;
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ack = false;
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}
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break;
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}
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}
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break;
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case TransferState::MemoryCard:
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{
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ack = TransferMemoryCard(m_selected_slot, data_in, data_out);
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if (!ack)
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{
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Log_DevPrintf("Memory card transfer ended");
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m_transfer_state = TransferState::Idle;
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}
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}
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break;
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case TransferState::ControllerCommand:
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{
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if (m_controller_transfer_step == 0) // Command byte
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{
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if (m_transfer_all_controllers)
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{
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// Unknown if 0x42 is the only valid command byte here, but other tested command bytes cause early aborts
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*data_out = GetMultitapIDByte();
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m_invalid_transfer_all_command = (data_in != 0x42);
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ack = true;
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}
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else
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{
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ack = TransferController(m_selected_slot, data_in, data_out);
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}
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m_controller_transfer_step++;
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}
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else if (m_controller_transfer_step == 1) // Request byte
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{
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if (m_transfer_all_controllers)
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{
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*data_out = GetStatusByte();
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ack = !m_invalid_transfer_all_command;
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m_selected_slot = 0;
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m_transfer_state = TransferState::AllControllers;
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}
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else
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{
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ack = TransferController(m_selected_slot, 0x00, data_out);
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m_transfer_state = TransferState::SingleController;
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}
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// Queue up request for next transfer cycle (not sure if this is always queued on invalid commands)
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m_transfer_all_controllers = (data_in & 0x01);
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m_controller_transfer_step = 0;
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}
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else
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{
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UnreachableCode();
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}
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}
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break;
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case TransferState::SingleController:
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{
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2021-03-01 22:59:59 +00:00
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// TODO: Check if the transfer buffer gets wiped when transitioning to/from this mode
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2021-01-21 07:59:40 +00:00
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ack = TransferController(m_selected_slot, data_in, data_out);
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if (!ack)
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{
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Log_DevPrintf("Controller transfer ended");
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m_transfer_state = TransferState::Idle;
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}
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}
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break;
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case TransferState::AllControllers:
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{
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// In this mode, we transfer until reaching 8 bytes or the controller finishes its response (no ack is returned).
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// The hardware is probably either latching the controller info halfword count or waiting for a transfer timeout
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// (timeouts might be possible due to buffered responses in this mode, and if the controllers are transferred in
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// parallel rather than sequentially like we're doing here). We'll just simplify this and check the ack return
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// value since our controller implementations are deterministic.
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*data_out = m_transfer_buffer[m_controller_transfer_step];
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ack = true;
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if (m_current_controller_done)
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m_transfer_buffer[m_controller_transfer_step] = 0xFF;
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else
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m_current_controller_done =
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!TransferController(m_selected_slot, data_in, &m_transfer_buffer[m_controller_transfer_step]);
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m_controller_transfer_step++;
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if (m_controller_transfer_step % 8 == 0)
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{
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m_current_controller_done = false;
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m_selected_slot = (m_selected_slot + 1) % 4;
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if (m_selected_slot == 0)
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ack = false;
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}
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}
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break;
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DefaultCaseIsUnreachable();
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}
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return ack;
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}
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