2019-09-09 07:01:26 +00:00
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#pragma once
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#include "bus.h"
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template<MemoryAccessType type, MemoryAccessSize size>
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bool Bus::DoRAMAccess(u32 offset, u32& value)
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{
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// TODO: Configurable mirroring.
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offset &= UINT32_C(0x1FFFFF);
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if constexpr (type == MemoryAccessType::Read)
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{
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if constexpr (size == MemoryAccessSize::Byte)
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{
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value = ZeroExtend32(m_ram[offset]);
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}
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else if constexpr (size == MemoryAccessSize::HalfWord)
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{
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u16 temp;
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std::memcpy(&temp, &m_ram[offset], sizeof(u16));
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value = ZeroExtend32(temp);
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}
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else if constexpr (size == MemoryAccessSize::Word)
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{
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std::memcpy(&value, &m_ram[offset], sizeof(u32));
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}
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}
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else
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{
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if constexpr (size == MemoryAccessSize::Byte)
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{
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m_ram[offset] = Truncate8(value);
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}
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else if constexpr (size == MemoryAccessSize::HalfWord)
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{
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const u16 temp = Truncate16(value);
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std::memcpy(&m_ram[offset], &temp, sizeof(u16));
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}
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else if constexpr (size == MemoryAccessSize::Word)
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{
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std::memcpy(&m_ram[offset], &value, sizeof(u32));
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}
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}
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return true;
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}
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template<MemoryAccessType type, MemoryAccessSize size>
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bool Bus::DoBIOSAccess(u32 offset, u32& value)
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{
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// TODO: Configurable mirroring.
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if constexpr (type == MemoryAccessType::Read)
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{
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offset &= UINT32_C(0x7FFFF);
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if constexpr (size == MemoryAccessSize::Byte)
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{
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value = ZeroExtend32(m_bios[offset]);
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}
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else if constexpr (size == MemoryAccessSize::HalfWord)
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{
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u16 temp;
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std::memcpy(&temp, &m_bios[offset], sizeof(u16));
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value = ZeroExtend32(temp);
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}
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else
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{
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std::memcpy(&value, &m_bios[offset], sizeof(u32));
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}
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}
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else
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{
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// Writes are ignored.
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}
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return true;
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}
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template<MemoryAccessType type, MemoryAccessSize size>
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bool Bus::DispatchAccess(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u32& value)
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{
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if (bus_address < 0x800000)
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{
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return DoRAMAccess<type, size>(bus_address, value);
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}
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2019-09-22 15:28:00 +00:00
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else if (bus_address < EXP1_BASE)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < (EXP1_BASE + EXP1_SIZE))
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{
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return (type == MemoryAccessType::Read) ? DoReadEXP1(size, bus_address & EXP1_MASK, value) :
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DoWriteEXP1(size, bus_address & EXP1_MASK, value);
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}
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2019-09-20 06:47:41 +00:00
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else if (bus_address < PAD_BASE)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < (PAD_BASE + PAD_SIZE))
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{
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return (type == MemoryAccessType::Read) ? DoReadPad(size, bus_address & PAD_MASK, value) :
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DoWritePad(size, bus_address & PAD_MASK, value);
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}
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2019-09-22 15:28:00 +00:00
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else if (bus_address < (SIO_BASE + SIO_SIZE))
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{
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return (type == MemoryAccessType::Read) ? DoReadSIO(size, bus_address & SIO_MASK, value) :
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DoWriteSIO(size, bus_address & SIO_MASK, value);
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}
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2019-09-17 06:26:00 +00:00
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else if (bus_address < INTERRUPT_CONTROLLER_BASE)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < (INTERRUPT_CONTROLLER_BASE + INTERRUPT_CONTROLLER_SIZE))
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{
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return (type == MemoryAccessType::Read) ?
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DoReadInterruptController(size, bus_address & INTERRUPT_CONTROLLER_MASK, value) :
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DoWriteInterruptController(size, bus_address & INTERRUPT_CONTROLLER_MASK, value);
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}
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2019-09-09 07:01:26 +00:00
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else if (bus_address < DMA_BASE)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < (DMA_BASE + DMA_SIZE))
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{
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return (type == MemoryAccessType::Read) ? DoReadDMA(size, bus_address & DMA_MASK, value) :
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DoWriteDMA(size, bus_address & DMA_MASK, value);
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}
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2019-09-20 13:40:19 +00:00
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else if (bus_address < TIMERS_BASE)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < (TIMERS_BASE + TIMERS_SIZE))
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{
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return (type == MemoryAccessType::Read) ? DoReadTimers(size, bus_address & TIMERS_MASK, value) :
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DoWriteTimers(size, bus_address & TIMERS_MASK, value);
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}
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2019-09-17 09:22:39 +00:00
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else if (bus_address < CDROM_BASE)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < (CDROM_BASE + GPU_SIZE))
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{
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return (type == MemoryAccessType::Read) ? DoReadCDROM(size, bus_address & CDROM_MASK, value) :
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DoWriteCDROM(size, bus_address & CDROM_MASK, value);
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}
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2019-09-11 04:01:19 +00:00
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else if (bus_address < GPU_BASE)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < (GPU_BASE + GPU_SIZE))
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{
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return (type == MemoryAccessType::Read) ? DoReadGPU(size, bus_address & GPU_MASK, value) :
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DoWriteGPU(size, bus_address & GPU_MASK, value);
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}
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2019-09-09 07:01:26 +00:00
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else if (bus_address < SPU_BASE)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < (SPU_BASE + SPU_SIZE))
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{
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return (type == MemoryAccessType::Read) ? ReadSPU(size, bus_address & SPU_MASK, value) :
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WriteSPU(size, bus_address & SPU_MASK, value);
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}
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else if (bus_address < EXP2_BASE)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < (EXP2_BASE + EXP2_SIZE))
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{
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2019-09-22 15:28:00 +00:00
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return (type == MemoryAccessType::Read) ? DoReadEXP2(size, bus_address & EXP2_MASK, value) :
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DoWriteEXP2(size, bus_address & EXP2_MASK, value);
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2019-09-09 07:01:26 +00:00
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}
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2019-09-14 03:22:05 +00:00
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else if (bus_address < BIOS_BASE)
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2019-09-09 07:01:26 +00:00
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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2019-09-14 03:22:05 +00:00
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else if (bus_address < (BIOS_BASE + BIOS_SIZE))
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2019-09-09 07:01:26 +00:00
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{
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2019-09-14 03:22:05 +00:00
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return DoBIOSAccess<type, size>(static_cast<u32>(bus_address - BIOS_BASE), value);
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2019-09-09 07:01:26 +00:00
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}
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else if (bus_address < 0x1FFE0000)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else if (bus_address < 0x1FFE0200) // I/O Ports (Cache Control)
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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else
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{
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return DoInvalidAccess(type, size, cpu_address, bus_address, value);
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}
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}
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