2023-10-03 14:39:18 +00:00
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// SPDX-FileCopyrightText: 2023 Connor McLaughlin <stenzek@gmail.com>
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// SPDX-License-Identifier: (GPL-3.0 OR CC-BY-NC-ND-4.0)
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#pragma once
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#include "cpu_newrec_compiler.h"
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#include <memory>
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#include "vixl/aarch64/assembler-aarch64.h"
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namespace CPU::NewRec {
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class AArch64Compiler final : public Compiler
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{
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public:
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AArch64Compiler();
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~AArch64Compiler() override;
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protected:
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const char* GetHostRegName(u32 reg) const override;
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const void* GetCurrentCodePointer() override;
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void LoadHostRegWithConstant(u32 reg, u32 val) override;
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void LoadHostRegFromCPUPointer(u32 reg, const void* ptr) override;
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void StoreConstantToCPUPointer(u32 val, const void* ptr) override;
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void StoreHostRegToCPUPointer(u32 reg, const void* ptr) override;
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void CopyHostReg(u32 dst, u32 src) override;
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void Reset(CodeCache::Block* block, u8* code_buffer, u32 code_buffer_space, u8* far_code_buffer, u32 far_code_space) override;
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void BeginBlock() override;
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void GenerateBlockProtectCheck(const u8* ram_ptr, const u8* shadow_ptr, u32 size) override;
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void GenerateICacheCheckAndUpdate() override;
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void GenerateCall(const void* func, s32 arg1reg = -1, s32 arg2reg = -1, s32 arg3reg = -1) override;
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void EndBlock(const std::optional<u32>& newpc, bool do_event_test) override;
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void EndBlockWithException(Exception excode) override;
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void EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test);
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const void* EndCompile(u32* code_size, u32* far_code_size) override;
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void Flush(u32 flags) override;
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void Compile_Fallback() override;
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void CheckBranchTarget(const vixl::aarch64::WRegister& pcreg);
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void Compile_jr(CompileFlags cf) override;
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void Compile_jalr(CompileFlags cf) override;
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void Compile_bxx(CompileFlags cf, BranchCondition cond) override;
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void Compile_addi(CompileFlags cf, bool overflow);
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void Compile_addi(CompileFlags cf) override;
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void Compile_addiu(CompileFlags cf) override;
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void Compile_slti(CompileFlags cf, bool sign);
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void Compile_slti(CompileFlags cf) override;
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void Compile_sltiu(CompileFlags cf) override;
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void Compile_andi(CompileFlags cf) override;
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void Compile_ori(CompileFlags cf) override;
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void Compile_xori(CompileFlags cf) override;
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void Compile_shift(CompileFlags cf, void (vixl::aarch64::Assembler::*op)(const vixl::aarch64::Register&,
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const vixl::aarch64::Register&, unsigned));
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void Compile_sll(CompileFlags cf) override;
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void Compile_srl(CompileFlags cf) override;
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void Compile_sra(CompileFlags cf) override;
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void Compile_variable_shift(CompileFlags cf,
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void (vixl::aarch64::Assembler::*op)(const vixl::aarch64::Register&,
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const vixl::aarch64::Register&,
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const vixl::aarch64::Register&),
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void (vixl::aarch64::Assembler::*op_const)(const vixl::aarch64::Register&,
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const vixl::aarch64::Register&, unsigned));
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void Compile_sllv(CompileFlags cf) override;
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void Compile_srlv(CompileFlags cf) override;
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void Compile_srav(CompileFlags cf) override;
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void Compile_mult(CompileFlags cf, bool sign);
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void Compile_mult(CompileFlags cf) override;
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void Compile_multu(CompileFlags cf) override;
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void Compile_div(CompileFlags cf) override;
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void Compile_divu(CompileFlags cf) override;
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void TestOverflow(const vixl::aarch64::WRegister& result);
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void Compile_dst_op(CompileFlags cf,
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void (vixl::aarch64::Assembler::*op)(const vixl::aarch64::Register&,
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const vixl::aarch64::Register&,
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const vixl::aarch64::Operand&),
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bool commutative, bool logical, bool overflow);
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void Compile_add(CompileFlags cf) override;
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void Compile_addu(CompileFlags cf) override;
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void Compile_sub(CompileFlags cf) override;
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void Compile_subu(CompileFlags cf) override;
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void Compile_and(CompileFlags cf) override;
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void Compile_or(CompileFlags cf) override;
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void Compile_xor(CompileFlags cf) override;
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void Compile_nor(CompileFlags cf) override;
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void Compile_slt(CompileFlags cf, bool sign);
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void Compile_slt(CompileFlags cf) override;
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void Compile_sltu(CompileFlags cf) override;
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vixl::aarch64::WRegister
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ComputeLoadStoreAddressArg(CompileFlags cf, const std::optional<VirtualMemoryAddress>& address,
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const std::optional<const vixl::aarch64::WRegister>& reg = std::nullopt);
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template<typename RegAllocFn>
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vixl::aarch64::WRegister GenerateLoad(const vixl::aarch64::WRegister& addr_reg, MemoryAccessSize size, bool sign,
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const RegAllocFn& dst_reg_alloc);
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void GenerateStore(const vixl::aarch64::WRegister& addr_reg, const vixl::aarch64::WRegister& value_reg,
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MemoryAccessSize size);
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void Compile_lxx(CompileFlags cf, MemoryAccessSize size, bool sign,
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const std::optional<VirtualMemoryAddress>& address) override;
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void Compile_lwx(CompileFlags cf, MemoryAccessSize size, bool sign,
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const std::optional<VirtualMemoryAddress>& address) override;
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void Compile_lwc2(CompileFlags cf, MemoryAccessSize size, bool sign,
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const std::optional<VirtualMemoryAddress>& address) override;
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void Compile_sxx(CompileFlags cf, MemoryAccessSize size, bool sign,
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const std::optional<VirtualMemoryAddress>& address) override;
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void Compile_swx(CompileFlags cf, MemoryAccessSize size, bool sign,
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const std::optional<VirtualMemoryAddress>& address) override;
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void Compile_swc2(CompileFlags cf, MemoryAccessSize size, bool sign,
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const std::optional<VirtualMemoryAddress>& address) override;
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void TestInterrupts(const vixl::aarch64::WRegister& sr);
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void Compile_mtc0(CompileFlags cf) override;
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void Compile_rfe(CompileFlags cf) override;
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void Compile_mfc2(CompileFlags cf) override;
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void Compile_mtc2(CompileFlags cf) override;
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void Compile_cop2(CompileFlags cf) override;
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void GeneratePGXPCallWithMIPSRegs(const void* func, u32 arg1val, Reg arg2reg = Reg::count,
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Reg arg3reg = Reg::count) override;
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private:
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void EmitMov(const vixl::aarch64::WRegister& dst, u32 val);
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void EmitCall(const void* ptr, bool force_inline = false);
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vixl::aarch64::Operand armCheckAddSubConstant(s32 val);
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vixl::aarch64::Operand armCheckAddSubConstant(u32 val);
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vixl::aarch64::Operand armCheckCompareConstant(s32 val);
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vixl::aarch64::Operand armCheckLogicalConstant(u32 val);
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void SwitchToFarCode(bool emit_jump, vixl::aarch64::Condition cond = vixl::aarch64::Condition::al);
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void SwitchToFarCodeIfBitSet(const vixl::aarch64::Register& reg, u32 bit);
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void SwitchToFarCodeIfRegZeroOrNonZero(const vixl::aarch64::Register& reg, bool nonzero);
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void SwitchToNearCode(bool emit_jump, vixl::aarch64::Condition cond = vixl::aarch64::Condition::al);
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void AssertRegOrConstS(CompileFlags cf) const;
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void AssertRegOrConstT(CompileFlags cf) const;
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vixl::aarch64::MemOperand MipsPtr(Reg r) const;
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vixl::aarch64::WRegister CFGetRegD(CompileFlags cf) const;
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vixl::aarch64::WRegister CFGetRegS(CompileFlags cf) const;
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vixl::aarch64::WRegister CFGetRegT(CompileFlags cf) const;
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vixl::aarch64::WRegister CFGetRegLO(CompileFlags cf) const;
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vixl::aarch64::WRegister CFGetRegHI(CompileFlags cf) const;
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void MoveSToReg(const vixl::aarch64::WRegister& dst, CompileFlags cf);
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void MoveTToReg(const vixl::aarch64::WRegister& dst, CompileFlags cf);
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void MoveMIPSRegToReg(const vixl::aarch64::WRegister& dst, Reg reg);
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2023-10-19 12:09:25 +00:00
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vixl::aarch64::Assembler m_emitter;
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vixl::aarch64::Assembler m_far_emitter;
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2023-10-03 14:39:18 +00:00
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vixl::aarch64::Assembler* armAsm;
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#ifdef VIXL_DEBUG
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std::unique_ptr<vixl::CodeBufferCheckScope> m_emitter_check;
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std::unique_ptr<vixl::CodeBufferCheckScope> m_far_emitter_check;
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#endif
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};
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} // namespace CPU::NewRec
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