2019-09-11 04:01:19 +00:00
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#pragma once
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#include "common/bitfield.h"
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#include "types.h"
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#include <array>
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class Bus;
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class DMA;
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class GPU
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{
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public:
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GPU();
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~GPU();
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bool Initialize(Bus* bus, DMA* dma);
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void Reset();
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u32 ReadRegister(u32 offset);
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void WriteRegister(u32 offset, u32 value);
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2019-09-11 04:59:41 +00:00
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// DMA access
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u32 DMARead();
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void DMAWrite(u32 value);
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2019-09-11 04:01:19 +00:00
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private:
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2019-09-11 06:04:31 +00:00
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static constexpr u32 MAX_GP0_COMMAND_LENGTH = 12;
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2019-09-11 04:59:41 +00:00
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enum class DMADirection : u32
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{
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Off = 0,
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FIFO = 1,
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CPUtoGP0 = 2,
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GPUREADtoCPU = 3
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};
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2019-09-11 04:01:19 +00:00
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void SoftReset();
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2019-09-11 04:59:41 +00:00
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void UpdateDMARequest();
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u32 ReadGPUREAD();
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2019-09-11 04:01:19 +00:00
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void WriteGP0(u32 value);
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void WriteGP1(u32 value);
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2019-09-11 06:04:31 +00:00
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// Rendering commands, returns false if not enough data is provided
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bool HandleRenderPolygonCommand();
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2019-09-11 04:01:19 +00:00
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Bus* m_bus = nullptr;
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DMA* m_dma = nullptr;
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union GPUSTAT
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{
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u32 bits;
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BitField<u32, u8, 0, 4> texture_page_x_base;
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BitField<u32, u8, 4, 1> texture_page_y_base;
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BitField<u32, u8, 5, 2> semi_transparency;
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BitField<u32, u8, 7, 2> texture_page_colors;
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BitField<u32, bool, 9, 1> dither_enable;
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BitField<u32, bool, 10, 1> draw_to_display_area;
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BitField<u32, bool, 11, 1> draw_set_mask_bit;
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BitField<u32, bool, 12, 1> draw_to_masked_pixels;
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BitField<u32, bool, 13, 1> interlaced_field;
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BitField<u32, bool, 14, 1> reverse_flag;
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BitField<u32, bool, 15, 1> texture_disable;
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BitField<u32, u8, 16, 1> horizontal_resolution_2;
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BitField<u32, u8, 17, 2> horizontal_resolution_1;
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BitField<u32, u8, 19, 1> vetical_resolution;
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BitField<u32, bool, 20, 1> pal_mode;
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BitField<u32, bool, 21, 1> display_area_color_depth_24;
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BitField<u32, bool, 22, 1> vertical_interlace;
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BitField<u32, bool, 23, 1> display_enable;
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BitField<u32, bool, 24, 1> interrupt_request;
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BitField<u32, bool, 25, 1> dma_data_request;
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BitField<u32, bool, 26, 1> ready_to_recieve_cmd;
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BitField<u32, bool, 27, 1> ready_to_send_vram;
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BitField<u32, bool, 28, 1> ready_to_recieve_dma;
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2019-09-11 04:59:41 +00:00
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BitField<u32, DMADirection, 29, 2> dma_direction;
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2019-09-11 04:01:19 +00:00
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BitField<u32, bool, 31, 1> drawing_even_line;
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} m_GPUSTAT = {};
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2019-09-11 06:04:31 +00:00
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struct TextureConfig
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{
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u8 window_mask_x; // in 8 pixel steps
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u8 window_mask_y; // in 8 pixel steps
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u8 window_offset_x; // in 8 pixel steps
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u8 window_offset_y; // in 8 pixel steps
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bool x_flip;
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bool y_flip;
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} m_texture_config = {};
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struct DrawingArea
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{
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u32 top_left_x, top_left_y;
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u32 bottom_right_x, bottom_right_y;
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} m_drawing_area = {};
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struct DrawingOffset
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{
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s32 x;
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s32 y;
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} m_drawing_offset = {};
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std::array<u32, MAX_GP0_COMMAND_LENGTH> m_GP0_command = {};
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u32 m_GP0_command_length = 0;
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2019-09-11 04:01:19 +00:00
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};
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