Duckstation/src/core/bus.inl

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#pragma once
#include "bus.h"
template<MemoryAccessType type, MemoryAccessSize size>
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TickCount Bus::DoRAMAccess(u32 offset, u32& value)
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{
// TODO: Configurable mirroring.
offset &= UINT32_C(0x1FFFFF);
if constexpr (type == MemoryAccessType::Read)
{
if constexpr (size == MemoryAccessSize::Byte)
{
value = ZeroExtend32(m_ram[offset]);
}
else if constexpr (size == MemoryAccessSize::HalfWord)
{
u16 temp;
std::memcpy(&temp, &m_ram[offset], sizeof(u16));
value = ZeroExtend32(temp);
}
else if constexpr (size == MemoryAccessSize::Word)
{
std::memcpy(&value, &m_ram[offset], sizeof(u32));
}
}
else
{
const u32 page_index = offset / CPU_CODE_CACHE_PAGE_SIZE;
if (m_ram_code_bits[page_index])
DoInvalidateCodeCache(page_index);
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if constexpr (size == MemoryAccessSize::Byte)
{
m_ram[offset] = Truncate8(value);
}
else if constexpr (size == MemoryAccessSize::HalfWord)
{
const u16 temp = Truncate16(value);
std::memcpy(&m_ram[offset], &temp, sizeof(u16));
}
else if constexpr (size == MemoryAccessSize::Word)
{
std::memcpy(&m_ram[offset], &value, sizeof(u32));
}
}
// Nocash docs say RAM takes 6 cycles to access.
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return (type == MemoryAccessType::Read) ? RAM_READ_ACCESS_DELAY : RAM_WRITE_ACCESS_DELAY;
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}
template<MemoryAccessType type, MemoryAccessSize size>
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TickCount Bus::DoBIOSAccess(u32 offset, u32& value)
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{
// TODO: Configurable mirroring.
if constexpr (type == MemoryAccessType::Read)
{
offset &= UINT32_C(0x7FFFF);
if constexpr (size == MemoryAccessSize::Byte)
{
value = ZeroExtend32(m_bios[offset]);
}
else if constexpr (size == MemoryAccessSize::HalfWord)
{
u16 temp;
std::memcpy(&temp, &m_bios[offset], sizeof(u16));
value = ZeroExtend32(temp);
}
else
{
std::memcpy(&value, &m_bios[offset], sizeof(u32));
}
}
else
{
// Writes are ignored.
}
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return m_bios_access_time[static_cast<u32>(size)];
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}
template<MemoryAccessType type, MemoryAccessSize size>
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TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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{
if (address < 0x800000)
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{
return DoRAMAccess<type, size>(address, value);
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}
else if (address < EXP1_BASE)
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{
return DoInvalidAccess(type, size, address, value);
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}
else if (address < (EXP1_BASE + EXP1_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadEXP1(size, address & EXP1_MASK);
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return m_exp1_access_time[static_cast<u32>(size)];
}
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else
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{
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DoWriteEXP1(size, address & EXP1_MASK, value);
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return 0;
}
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}
else if (address < MEMCTRL_BASE)
{
return DoInvalidAccess(type, size, address, value);
}
else if (address < (MEMCTRL_BASE + MEMCTRL_SIZE))
{
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if constexpr (type == MemoryAccessType::Read)
value = DoReadMemoryControl(size, address & PAD_MASK);
else
DoWriteMemoryControl(size, address & PAD_MASK, value);
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return 0;
}
else if (address < (PAD_BASE + PAD_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
value = DoReadPad(size, address & PAD_MASK);
else
DoWritePad(size, address & PAD_MASK, value);
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return 0;
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}
else if (address < (SIO_BASE + SIO_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
value = DoReadSIO(size, address & SIO_MASK);
else
DoWriteSIO(size, address & SIO_MASK, value);
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return 0;
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}
else if (address < (MEMCTRL2_BASE + MEMCTRL2_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
value = DoReadMemoryControl2(size, address & PAD_MASK);
else
DoWriteMemoryControl2(size, address & PAD_MASK, value);
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return 0;
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}
else if (address < (INTERRUPT_CONTROLLER_BASE + INTERRUPT_CONTROLLER_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
value = DoReadInterruptController(size, address & INTERRUPT_CONTROLLER_MASK);
else
DoWriteInterruptController(size, address & INTERRUPT_CONTROLLER_MASK, value);
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return 0;
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}
else if (address < (DMA_BASE + DMA_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
value = DoReadDMA(size, address & DMA_MASK);
else
DoWriteDMA(size, address & DMA_MASK, value);
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return 0;
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}
else if (address < (TIMERS_BASE + TIMERS_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
value = DoReadTimers(size, address & TIMERS_MASK);
else
DoWriteTimers(size, address & TIMERS_MASK, value);
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return 0;
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}
else if (address < CDROM_BASE)
{
return DoInvalidAccess(type, size, address, value);
}
else if (address < (CDROM_BASE + GPU_SIZE))
{
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadCDROM(size, address & CDROM_MASK);
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return m_cdrom_access_time[static_cast<u32>(size)];
}
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else
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{
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DoWriteCDROM(size, address & CDROM_MASK, value);
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return 0;
}
}
else if (address < (GPU_BASE + GPU_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
value = DoReadGPU(size, address & GPU_MASK);
else
DoWriteGPU(size, address & GPU_MASK, value);
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return 0;
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}
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else if (address < (MDEC_BASE + MDEC_SIZE))
{
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if constexpr (type == MemoryAccessType::Read)
value = DoReadMDEC(size, address & MDEC_MASK);
else
DoWriteMDEC(size, address & MDEC_MASK, value);
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return 0;
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}
else if (address < SPU_BASE)
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{
return DoInvalidAccess(type, size, address, value);
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}
else if (address < (SPU_BASE + SPU_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadSPU(size, address & SPU_MASK);
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return m_spu_access_time[static_cast<u32>(size)];
}
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else
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{
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DoWriteSPU(size, address & SPU_MASK, value);
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return 0;
}
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}
else if (address < EXP2_BASE)
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{
return DoInvalidAccess(type, size, address, value);
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}
else if (address < (EXP2_BASE + EXP2_SIZE))
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{
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadEXP2(size, address & EXP2_MASK);
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return m_exp2_access_time[static_cast<u32>(size)];
}
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else
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{
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DoWriteEXP2(size, address & EXP2_MASK, value);
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return 0;
}
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}
else if (address < BIOS_BASE)
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{
return DoInvalidAccess(type, size, address, value);
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}
else if (address < (BIOS_BASE + BIOS_SIZE))
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{
return DoBIOSAccess<type, size>(static_cast<u32>(address - BIOS_BASE), value);
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}
else
{
return DoInvalidAccess(type, size, address, value);
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}
}