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PGXP: Fix MFC0/MTC0

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Doubt it'll change anything.
This commit is contained in:
Connor McLaughlin 2021-02-18 01:15:18 +10:00
parent a722fd6b53
commit 0bfa1bf873
3 changed files with 5 additions and 23 deletions
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4
src/core/cpu_core.cpp
View file

@ -1303,7 +1303,7 @@ restart_instruction:
const std::optional<u32> value = ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue())); const std::optional<u32> value = ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()));
if constexpr (pgxp_mode == PGXPMode::CPU) if constexpr (pgxp_mode == PGXPMode::CPU)
PGXP::CPU_MFC0(inst.bits, value.value_or(0), ReadReg(inst.i.rs)); PGXP::CPU_MFC0(inst.bits, value.value_or(0));
if (value) if (value)
WriteRegDelayed(inst.r.rt, value.value()); WriteRegDelayed(inst.r.rt, value.value());
@ -1319,7 +1319,7 @@ restart_instruction:
if constexpr (pgxp_mode == PGXPMode::CPU) if constexpr (pgxp_mode == PGXPMode::CPU)
{ {
PGXP::CPU_MTC0(inst.bits, ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue())).value_or(0), PGXP::CPU_MTC0(inst.bits, ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue())).value_or(0),
ReadReg(inst.i.rs)); ReadReg(inst.i.rt));
} }
} }
break; break;

20
src/core/pgxp.cpp
View file

@ -1876,12 +1876,12 @@ void CPU_MTLO(u32 instr, u32 rdVal)
CPU_Lo = CPU_reg[rd(instr)]; CPU_Lo = CPU_reg[rd(instr)];
} }
void CPU_MFC0(u32 instr, u32 rtVal, u32 rdVal) void CPU_MFC0(u32 instr, u32 rdVal)
{ {
// CPU[Rt] = CP0[Rd] // CPU[Rt] = CP0[Rd]
Validate(&CP0_reg[rd(instr)], rdVal); Validate(&CP0_reg[rd(instr)], rdVal);
CPU_reg[rt(instr)] = CP0_reg[rd(instr)]; CPU_reg[rt(instr)] = CP0_reg[rd(instr)];
CPU_reg[rt(instr)].value = rtVal; CPU_reg[rt(instr)].value = rdVal;
} }
void CPU_MTC0(u32 instr, u32 rdVal, u32 rtVal) void CPU_MTC0(u32 instr, u32 rdVal, u32 rtVal)
@ -1892,20 +1892,4 @@ void CPU_MTC0(u32 instr, u32 rdVal, u32 rtVal)
CP0_reg[rd(instr)].value = rdVal; CP0_reg[rd(instr)].value = rdVal;
} }
void CPU_CFC0(u32 instr, u32 rtVal, u32 rdVal)
{
// CPU[Rt] = CP0[Rd]
Validate(&CP0_reg[rd(instr)], rdVal);
CPU_reg[rt(instr)] = CP0_reg[rd(instr)];
CPU_reg[rt(instr)].value = rtVal;
}
void CPU_CTC0(u32 instr, u32 rdVal, u32 rtVal)
{
// CP0[Rd] = CPU[Rt]
Validate(&CPU_reg[rt(instr)], rtVal);
CP0_reg[rd(instr)] = CPU_reg[rt(instr)];
CP0_reg[rd(instr)].value = rdVal;
}
} // namespace PGXP } // namespace PGXP

4
src/core/pgxp.h
View file

@ -98,9 +98,7 @@ void CPU_MFLO(u32 instr, u32 loVal);
void CPU_MTLO(u32 instr, u32 rdVal); void CPU_MTLO(u32 instr, u32 rdVal);
// CP0 Data transfer tracking // CP0 Data transfer tracking
void CPU_MFC0(u32 instr, u32 rtVal, u32 rdVal); void CPU_MFC0(u32 instr, u32 rdVal);
void CPU_MTC0(u32 instr, u32 rdVal, u32 rtVal); void CPU_MTC0(u32 instr, u32 rdVal, u32 rtVal);
void CPU_CFC0(u32 instr, u32 rtVal, u32 rdVal);
void CPU_CTC0(u32 instr, u32 rdVal, u32 rtVal);
} // namespace PGXP } // namespace PGXP