From 17b97368995f616886da89bfa888645c02a275c3 Mon Sep 17 00:00:00 2001 From: Stenzek Date: Thu, 18 Apr 2024 20:38:01 +1000 Subject: [PATCH] Misc: Use a 128b cache line size on Apple Silicon Turns out it's not 64 bytes like I assumed. The things you learn. --- src/common/types.h | 7 +++++++ src/core/gpu_backend.h | 4 ++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/common/types.h b/src/common/types.h index 600a06c8c..c016931d8 100644 --- a/src/common/types.h +++ b/src/common/types.h @@ -185,6 +185,13 @@ static constexpr u32 HOST_PAGE_MASK = HOST_PAGE_SIZE - 1; static constexpr u32 HOST_PAGE_SHIFT = 12; #endif +// Host cache line sizes. +#if defined(__APPLE__) && defined(__aarch64__) +static constexpr u32 HOST_CACHE_LINE_SIZE = 128; // Apple Silicon uses 128b cache lines. +#else +static constexpr u32 HOST_CACHE_LINE_SIZE = 64; // Everything else is 64b. +#endif + // Enum class bitwise operators #define IMPLEMENT_ENUM_CLASS_BITWISE_OPERATORS(type_) \ ALWAYS_INLINE constexpr type_ operator&(type_ lhs, type_ rhs) \ diff --git a/src/core/gpu_backend.h b/src/core/gpu_backend.h index 3115b4d22..1fc59c5db 100644 --- a/src/core/gpu_backend.h +++ b/src/core/gpu_backend.h @@ -83,8 +83,8 @@ protected: }; FixedHeapArray m_command_fifo_data; - alignas(64) std::atomic m_command_fifo_read_ptr{0}; - alignas(64) std::atomic m_command_fifo_write_ptr{0}; + alignas(HOST_CACHE_LINE_SIZE) std::atomic m_command_fifo_read_ptr{0}; + alignas(HOST_CACHE_LINE_SIZE) std::atomic m_command_fifo_write_ptr{0}; }; #ifdef _MSC_VER