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CPU/PGXP: Purge macros
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@ -81,13 +81,17 @@ static PGXP_value& ValidateAndGetRtValue(Instruction instr, u32 rtVal);
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static PGXP_value& ValidateAndGetRsValue(Instruction instr, u32 rsVal);
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static void SetRtValue(Instruction instr, const PGXP_value& val);
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static void SetRtValue(Instruction instr, const PGXP_value& val, u32 rtVal);
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static PGXP_value& GetSXY0();
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static PGXP_value& GetSXY1();
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static PGXP_value& GetSXY2();
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static PGXP_value& PushSXY();
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static PGXP_value* GetPtr(u32 addr);
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static const PGXP_value& ValidateAndLoadMem(u32 addr, u32 value);
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static void ValidateAndLoadMem16(PGXP_value* dest, u32 addr, u32 value, bool sign);
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static void CPU_MTC2_int(const PGXP_value& value, u32 reg, u32 val);
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static void CPU_MTC2(u32 reg, const PGXP_value& value, u32 val);
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static void CPU_BITWISE(Instruction instr, u32 rdVal, u32 rsVal, u32 rtVal);
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static void CPU_SLL(Instruction instr, u32 rtVal, u32 sh);
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static void CPU_SRx(Instruction instr, u32 rtVal, u32 sh, bool sign, bool is_variable);
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@ -189,18 +193,6 @@ void CPU::PGXP::Shutdown()
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std::memset(g_state.pgxp_cop0, 0, sizeof(g_state.pgxp_cop0));
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}
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#define SX0 (g_state.pgxp_gte[12].x)
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#define SY0 (g_state.pgxp_gte[12].y)
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#define SX1 (g_state.pgxp_gte[13].x)
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#define SY1 (g_state.pgxp_gte[13].y)
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#define SX2 (g_state.pgxp_gte[14].x)
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#define SY2 (g_state.pgxp_gte[14].y)
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#define SXY0 (g_state.pgxp_gte[12])
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#define SXY1 (g_state.pgxp_gte[13])
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#define SXY2 (g_state.pgxp_gte[14])
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#define SXYP (g_state.pgxp_gte[15])
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ALWAYS_INLINE_RELEASE void CPU::PGXP::MakeValid(PGXP_value* pV, u32 psxV)
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{
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if ((pV->flags & VALID_XY) == VALID_XY)
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@ -271,6 +263,28 @@ ALWAYS_INLINE void CPU::PGXP::SetRtValue(Instruction instr, const PGXP_value& va
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prtVal.value = rtVal;
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}
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ALWAYS_INLINE CPU::PGXP_value& CPU::PGXP::GetSXY0()
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{
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return g_state.pgxp_gte[12];
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}
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ALWAYS_INLINE CPU::PGXP_value& CPU::PGXP::GetSXY1()
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{
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return g_state.pgxp_gte[13];
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}
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ALWAYS_INLINE CPU::PGXP_value& CPU::PGXP::GetSXY2()
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{
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return g_state.pgxp_gte[14];
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}
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ALWAYS_INLINE CPU::PGXP_value& CPU::PGXP::PushSXY()
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{
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g_state.pgxp_gte[12] = g_state.pgxp_gte[13];
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g_state.pgxp_gte[13] = g_state.pgxp_gte[14];
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return g_state.pgxp_gte[14];
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}
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ALWAYS_INLINE_RELEASE CPU::PGXP_value* CPU::PGXP::GetPtr(u32 addr)
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{
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#if 0
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@ -469,26 +483,22 @@ void CPU::PGXP::LogValueStr(SmallStringBase& str, const char* name, u32 rval, co
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void CPU::PGXP::GTE_RTPS(float x, float y, float z, u32 value)
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{
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// push values down FIFO
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SXY0 = SXY1;
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SXY1 = SXY2;
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SXY2.x = x;
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SXY2.y = y;
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SXY2.z = z;
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SXY2.value = value;
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SXY2.flags = VALID_ALL;
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PGXP_value& pvalue = PushSXY();
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pvalue.x = x;
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pvalue.y = y;
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pvalue.z = z;
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pvalue.value = value;
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pvalue.flags = VALID_ALL;
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if (g_settings.gpu_pgxp_vertex_cache)
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CacheVertex(value, SXY2);
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CacheVertex(value, pvalue);
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}
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#define VX(n) (psxRegs.CP2D.p[n << 1].sw.l)
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#define VY(n) (psxRegs.CP2D.p[n << 1].sw.h)
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#define VZ(n) (psxRegs.CP2D.p[(n << 1) + 1].sw.l)
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int CPU::PGXP::GTE_NCLIP_valid(u32 sxy0, u32 sxy1, u32 sxy2)
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{
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PGXP_value& SXY0 = GetSXY0();
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PGXP_value& SXY1 = GetSXY1();
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PGXP_value& SXY2 = GetSXY2();
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Validate(&SXY0, sxy0);
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Validate(&SXY1, sxy1);
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Validate(&SXY2, sxy2);
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@ -499,48 +509,47 @@ int CPU::PGXP::GTE_NCLIP_valid(u32 sxy0, u32 sxy1, u32 sxy2)
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float CPU::PGXP::GTE_NCLIP()
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{
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float nclip = ((SX0 * SY1) + (SX1 * SY2) + (SX2 * SY0) - (SX0 * SY2) - (SX1 * SY0) - (SX2 * SY1));
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const PGXP_value& SXY0 = GetSXY0();
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const PGXP_value& SXY1 = GetSXY1();
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const PGXP_value& SXY2 = GetSXY2();
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float nclip = ((SXY0.x * SXY1.y) + (SXY1.x * SXY2.y) + (SXY2.x * SXY0.y) - (SXY0.x * SXY2.y) - (SXY1.x * SXY0.y) -
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(SXY2.x * SXY1.y));
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// ensure fractional values are not incorrectly rounded to 0
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float nclipAbs = std::abs(nclip);
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if ((0.1f < nclipAbs) && (nclipAbs < 1.f))
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nclip += (nclip < 0.f ? -1 : 1);
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// float AX = SX1 - SX0;
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// float AY = SY1 - SY0;
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// float BX = SX2 - SX0;
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// float BY = SY2 - SY0;
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//// normalise A and B
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// float mA = sqrt((AX*AX) + (AY*AY));
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// float mB = sqrt((BX*BX) + (BY*BY));
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//// calculate AxB to get Z component of C
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// float CZ = ((AX * BY) - (AY * BX)) * (1 << 12);
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const float nclip_abs = std::abs(nclip);
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if (0.1f < nclip_abs && nclip_abs < 1.0f)
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nclip += (nclip < 0.0f ? -1.0f : 1.0f);
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return nclip;
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}
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ALWAYS_INLINE_RELEASE void CPU::PGXP::CPU_MTC2_int(const PGXP_value& value, u32 reg, u32 val)
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ALWAYS_INLINE_RELEASE void CPU::PGXP::CPU_MTC2(u32 reg, const PGXP_value& value, u32 val)
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{
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switch (reg)
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{
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case 15:
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{
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// push FIFO
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SXY0 = SXY1;
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SXY1 = SXY2;
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PGXP_value& SXY2 = PushSXY();
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SXY2 = value;
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SXYP = SXY2;
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break;
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case 31:
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return;
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}
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}
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PGXP_value& gteVal = g_state.pgxp_gte[reg];
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gteVal = value;
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gteVal.value = val;
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// read-only registers
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case 29:
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case 31:
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{
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return;
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}
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default:
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{
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PGXP_value& gteVal = g_state.pgxp_gte[reg];
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gteVal = value;
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gteVal.value = val;
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return;
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}
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}
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}
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////////////////////////////////////
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@ -565,7 +574,7 @@ void CPU::PGXP::CPU_MTC2(Instruction instr, u32 rtVal)
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LOG_VALUES_C1(instr.r.rt.GetValue(), rtVal);
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PGXP_value& prtVal = ValidateAndGetRtValue(instr, rtVal);
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CPU_MTC2_int(prtVal, idx, rtVal);
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CPU_MTC2(idx, prtVal, rtVal);
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}
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////////////////////////////////////
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@ -577,7 +586,7 @@ void CPU::PGXP::CPU_LWC2(Instruction instr, u32 addr, u32 rtVal)
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LOG_VALUES_LOAD(addr, rtVal);
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const PGXP_value& pMem = ValidateAndLoadMem(addr, rtVal);
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CPU_MTC2_int(pMem, static_cast<u32>(instr.r.rt.GetValue()), rtVal);
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CPU_MTC2(static_cast<u32>(instr.r.rt.GetValue()), pMem, rtVal);
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}
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void CPU::PGXP::CPU_SWC2(Instruction instr, u32 addr, u32 rtVal)
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