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PGXP: Combine instr and rtVal parameters for CPU_LUI

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This commit is contained in:
Connor McLaughlin 2021-02-18 00:47:38 +10:00
parent bc021ddfd9
commit 1b881fc60b
4 changed files with 7 additions and 12 deletions
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2
src/core/cpu_core.cpp
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@ -939,7 +939,7 @@ restart_instruction:
WriteReg(inst.i.rt, value); WriteReg(inst.i.rt, value);
if constexpr (pgxp_mode >= PGXPMode::CPU) if constexpr (pgxp_mode >= PGXPMode::CPU)
PGXP::CPU_LUI(inst.bits, value); PGXP::CPU_LUI(inst.bits);
} }
break; break;

11
src/core/cpu_recompiler_code_generator.cpp
View file

@ -2274,16 +2274,11 @@ bool CodeGenerator::Compile_lui(const CodeBlockInstruction& cbi)
{ {
InstructionPrologue(cbi, 1); InstructionPrologue(cbi, 1);
if (g_settings.UsingPGXPCPUMode())
EmitFunctionCall(nullptr, &PGXP::CPU_LUI, Value::FromConstantU32(cbi.instruction.bits));
// rt <- (imm << 16) // rt <- (imm << 16)
const u32 value = cbi.instruction.i.imm_zext32() << 16; const u32 value = cbi.instruction.i.imm_zext32() << 16;
if (g_settings.UsingPGXPCPUMode())
{
// TODO: rtVal can be skipped here, and probably worthwhile given this is a common instruction.
EmitFunctionCall(nullptr, &PGXP::CPU_LUI, Value::FromConstantU32(cbi.instruction.bits),
Value::FromConstantU32(value));
}
m_register_cache.WriteGuestRegister(cbi.instruction.i.rt, Value::FromConstantU32(value)); m_register_cache.WriteGuestRegister(cbi.instruction.i.rt, Value::FromConstantU32(value));
SpeculativeWriteReg(cbi.instruction.i.rt, value); SpeculativeWriteReg(cbi.instruction.i.rt, value);

4
src/core/pgxp.cpp
View file

@ -1045,13 +1045,13 @@ void CPU_SLTIU(u32 instr, u32 rtVal, u32 rsVal)
//////////////////////////////////// ////////////////////////////////////
// Load Upper // Load Upper
//////////////////////////////////// ////////////////////////////////////
void CPU_LUI(u32 instr, u32 rtVal) void CPU_LUI(u32 instr)
{ {
// Rt = Imm << 16 // Rt = Imm << 16
CPU_reg[rt(instr)] = PGXP_value_zero; CPU_reg[rt(instr)] = PGXP_value_zero;
CPU_reg[rt(instr)].y = (float)(s16)imm(instr); CPU_reg[rt(instr)].y = (float)(s16)imm(instr);
CPU_reg[rt(instr)].hFlags = VALID_HALF; CPU_reg[rt(instr)].hFlags = VALID_HALF;
CPU_reg[rt(instr)].value = rtVal; CPU_reg[rt(instr)].value = static_cast<u32>(imm(instr)) << 16;
CPU_reg[rt(instr)].flags = VALID_01; CPU_reg[rt(instr)].flags = VALID_01;
} }

2
src/core/pgxp.h
View file

@ -63,7 +63,7 @@ void CPU_SLTI(u32 instr, u32 rtVal, u32 rsVal);
void CPU_SLTIU(u32 instr, u32 rtVal, u32 rsVal); void CPU_SLTIU(u32 instr, u32 rtVal, u32 rsVal);
// Load Upper // Load Upper
void CPU_LUI(u32 instr, u32 rtVal); void CPU_LUI(u32 instr);
// Register Arithmetic // Register Arithmetic
void CPU_ADD(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal); void CPU_ADD(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal);