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CPU/Interpreter: Out of range cop0 reads should be nops
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dd5277321b
commit
22fdd80cc3
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@ -380,7 +380,7 @@ ALWAYS_INLINE_RELEASE static void WriteRegDelayed(Reg rd, u32 value)
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g_state.next_load_delay_value = value;
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g_state.next_load_delay_value = value;
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}
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}
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ALWAYS_INLINE_RELEASE static std::optional<u32> ReadCop0Reg(Cop0Reg reg)
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ALWAYS_INLINE_RELEASE static u32 ReadCop0Reg(Cop0Reg reg)
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{
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{
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switch (reg)
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switch (reg)
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{
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{
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@ -418,8 +418,8 @@ ALWAYS_INLINE_RELEASE static std::optional<u32> ReadCop0Reg(Cop0Reg reg)
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return g_state.cop0_regs.PRID;
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return g_state.cop0_regs.PRID;
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default:
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default:
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Log_DevPrintf("Unknown COP0 reg %u", ZeroExtend32(static_cast<u8>(reg)));
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Log_WarningPrintf("Unknown COP0 reg read %u", ZeroExtend32(static_cast<u8>(reg)));
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return std::nullopt;
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return 0;
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}
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}
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}
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}
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@ -1311,15 +1311,12 @@ restart_instruction:
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{
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{
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case CopCommonInstruction::mfcn:
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case CopCommonInstruction::mfcn:
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{
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{
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const std::optional<u32> value = ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()));
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const u32 value = ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()));
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if constexpr (pgxp_mode == PGXPMode::CPU)
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if constexpr (pgxp_mode == PGXPMode::CPU)
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PGXP::CPU_MFC0(inst.bits, value.value_or(0));
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PGXP::CPU_MFC0(inst.bits, value);
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if (value)
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WriteRegDelayed(inst.r.rt, value);
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WriteRegDelayed(inst.r.rt, value.value());
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else
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RaiseException(Exception::RI);
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}
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}
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break;
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break;
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@ -1328,10 +1325,7 @@ restart_instruction:
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WriteCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()), ReadReg(inst.r.rt));
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WriteCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()), ReadReg(inst.r.rt));
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if constexpr (pgxp_mode == PGXPMode::CPU)
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if constexpr (pgxp_mode == PGXPMode::CPU)
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{
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PGXP::CPU_MTC0(inst.bits, ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue())), ReadReg(inst.i.rt));
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PGXP::CPU_MTC0(inst.bits, ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue())).value_or(0),
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ReadReg(inst.i.rt));
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}
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}
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}
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break;
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break;
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