mirror of
https://github.com/RetroDECK/Duckstation.git
synced 2024-11-25 15:15:40 +00:00
DMA: Convert to namespace
This commit is contained in:
Connor McLaughlin
parent
d096a09ed8
commit
3acf569d67
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@ -1331,13 +1331,13 @@ ALWAYS_INLINE static TickCount DoDMAAccess(u32 offset, u32& value)
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{
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if constexpr (type == MemoryAccessType::Read)
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{
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value = g_dma.ReadRegister(FIXUP_WORD_OFFSET(size, offset));
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value = DMA::ReadRegister(FIXUP_WORD_OFFSET(size, offset));
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value = FIXUP_WORD_READ_VALUE(size, offset, value);
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return 2;
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}
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else
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{
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g_dma.WriteRegister(FIXUP_WORD_OFFSET(size, offset), FIXUP_WORD_WRITE_VALUE(size, offset, value));
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DMA::WriteRegister(FIXUP_WORD_OFFSET(size, offset), FIXUP_WORD_WRITE_VALUE(size, offset, value));
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return 0;
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}
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}
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@ -1172,7 +1172,7 @@ void CDROM::UpdateStatusRegister()
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s_status.DRQSTS = !s_data_fifo.IsEmpty();
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s_status.BUSYSTS = HasPendingCommand();
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g_dma.SetRequest(DMA::Channel::CDROM, s_status.DRQSTS);
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DMA::SetRequest(DMA::Channel::CDROM, s_status.DRQSTS);
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}
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void CDROM::UpdateInterruptRequest()
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341
src/core/dma.cpp
341
src/core/dma.cpp
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@ -4,6 +4,7 @@
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#include "dma.h"
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#include "bus.h"
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#include "cdrom.h"
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#include "common/bitfield.h"
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#include "common/log.h"
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#include "common/string_util.h"
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#include "cpu_code_cache.h"
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@ -17,84 +18,238 @@
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#include "spu.h"
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#include "system.h"
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#include "util/state_wrapper.h"
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#include <array>
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#include <memory>
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#include <vector>
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Log_SetChannel(DMA);
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static u32 GetAddressMask()
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namespace DMA {
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enum class SyncMode : u32
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{
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Manual = 0,
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Request = 1,
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LinkedList = 2,
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Reserved = 3
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};
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static constexpr PhysicalMemoryAddress BASE_ADDRESS_MASK = UINT32_C(0x00FFFFFF);
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static constexpr PhysicalMemoryAddress ADDRESS_MASK = UINT32_C(0x001FFFFC);
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static u32 GetAddressMask();
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static void ClearState();
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// is everything enabled for a channel to operate?
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static bool CanTransferChannel(Channel channel, bool ignore_halt);
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static bool IsTransferHalted();
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static void UpdateIRQ();
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// returns false if the DMA should now be halted
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static TickCount GetTransferSliceTicks();
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static TickCount GetTransferHaltTicks();
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static bool TransferChannel(Channel channel);
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static void HaltTransfer(TickCount duration);
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static void UnhaltTransfer(void*, TickCount ticks, TickCount ticks_late);
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// from device -> memory
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static TickCount TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u32 word_count);
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// from memory -> device
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static TickCount TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u32 word_count);
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// configuration
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static TickCount s_max_slice_ticks = 1000;
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static TickCount s_halt_ticks = 100;
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static std::vector<u32> s_transfer_buffer;
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static std::unique_ptr<TimingEvent> s_unhalt_event;
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static TickCount s_halt_ticks_remaining = 0;
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struct ChannelState
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{
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u32 base_address = 0;
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union BlockControl
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{
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u32 bits;
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union
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{
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BitField<u32, u32, 0, 16> word_count;
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u32 GetWordCount() const { return (word_count == 0) ? 0x10000 : word_count; }
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} manual;
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union
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{
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BitField<u32, u32, 0, 16> block_size;
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BitField<u32, u32, 16, 16> block_count;
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u32 GetBlockSize() const { return (block_size == 0) ? 0x10000 : block_size; }
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u32 GetBlockCount() const { return (block_count == 0) ? 0x10000 : block_count; }
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} request;
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} block_control = {};
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union ChannelControl
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{
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u32 bits;
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BitField<u32, bool, 0, 1> copy_to_device;
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BitField<u32, bool, 1, 1> address_step_reverse;
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BitField<u32, bool, 8, 1> chopping_enable;
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BitField<u32, SyncMode, 9, 2> sync_mode;
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BitField<u32, u32, 16, 3> chopping_dma_window_size;
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BitField<u32, u32, 20, 3> chopping_cpu_window_size;
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BitField<u32, bool, 24, 1> enable_busy;
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BitField<u32, bool, 28, 1> start_trigger;
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static constexpr u32 WRITE_MASK = 0b01110001'01110111'00000111'00000011;
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} channel_control = {};
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bool request = false;
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};
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static std::array<ChannelState, NUM_CHANNELS> s_state;
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union DPCR
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{
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u32 bits;
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BitField<u32, u8, 0, 3> MDECin_priority;
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BitField<u32, bool, 3, 1> MDECin_master_enable;
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BitField<u32, u8, 4, 3> MDECout_priority;
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BitField<u32, bool, 7, 1> MDECout_master_enable;
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BitField<u32, u8, 8, 3> GPU_priority;
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BitField<u32, bool, 10, 1> GPU_master_enable;
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BitField<u32, u8, 12, 3> CDROM_priority;
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BitField<u32, bool, 15, 1> CDROM_master_enable;
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BitField<u32, u8, 16, 3> SPU_priority;
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BitField<u32, bool, 19, 1> SPU_master_enable;
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BitField<u32, u8, 20, 3> PIO_priority;
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BitField<u32, bool, 23, 1> PIO_master_enable;
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BitField<u32, u8, 24, 3> OTC_priority;
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BitField<u32, bool, 27, 1> OTC_master_enable;
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BitField<u32, u8, 28, 3> priority_offset;
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BitField<u32, bool, 31, 1> unused;
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u8 GetPriority(Channel channel) const { return ((bits >> (static_cast<u8>(channel) * 4)) & u32(3)); }
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bool GetMasterEnable(Channel channel) const
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{
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) * 4 + 3)) & u32(1));
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}
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};
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static DPCR s_DPCR = {};
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static constexpr u32 DICR_WRITE_MASK = 0b00000000'11111111'10000000'00111111;
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static constexpr u32 DICR_RESET_MASK = 0b01111111'00000000'00000000'00000000;
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union DICR
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{
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u32 bits;
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BitField<u32, bool, 15, 1> force_irq;
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BitField<u32, bool, 16, 1> MDECin_irq_enable;
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BitField<u32, bool, 17, 1> MDECout_irq_enable;
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BitField<u32, bool, 18, 1> GPU_irq_enable;
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BitField<u32, bool, 19, 1> CDROM_irq_enable;
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BitField<u32, bool, 20, 1> SPU_irq_enable;
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BitField<u32, bool, 21, 1> PIO_irq_enable;
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BitField<u32, bool, 22, 1> OTC_irq_enable;
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BitField<u32, bool, 23, 1> master_enable;
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BitField<u32, bool, 24, 1> MDECin_irq_flag;
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BitField<u32, bool, 25, 1> MDECout_irq_flag;
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BitField<u32, bool, 26, 1> GPU_irq_flag;
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BitField<u32, bool, 27, 1> CDROM_irq_flag;
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BitField<u32, bool, 28, 1> SPU_irq_flag;
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BitField<u32, bool, 29, 1> PIO_irq_flag;
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BitField<u32, bool, 30, 1> OTC_irq_flag;
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BitField<u32, bool, 31, 1> master_flag;
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bool IsIRQEnabled(Channel channel) const
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{
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 16)) & u32(1));
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}
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bool GetIRQFlag(Channel channel) const
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{
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 24)) & u32(1));
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}
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void SetIRQFlag(Channel channel) { bits |= (u32(1) << (static_cast<u8>(channel) + 24)); }
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void ClearIRQFlag(Channel channel) { bits &= ~(u32(1) << (static_cast<u8>(channel) + 24)); }
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void UpdateMasterFlag()
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{
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master_flag = master_enable && ((((bits >> 16) & u32(0b1111111)) & ((bits >> 24) & u32(0b1111111))) != 0);
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}
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};
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static DICR s_DICR = {};
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}; // namespace DMA
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u32 DMA::GetAddressMask()
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{
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return Bus::g_ram_mask & 0xFFFFFFFCu;
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}
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DMA g_dma;
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DMA::DMA() = default;
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DMA::~DMA() = default;
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void DMA::Initialize()
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{
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m_max_slice_ticks = g_settings.dma_max_slice_ticks;
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m_halt_ticks = g_settings.dma_halt_ticks;
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m_transfer_buffer.resize(32);
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m_unhalt_event = TimingEvents::CreateTimingEvent(
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"DMA Transfer Unhalt", 1, m_max_slice_ticks,
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[](void* param, TickCount ticks, TickCount ticks_late) { static_cast<DMA*>(param)->UnhaltTransfer(ticks); }, this,
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false);
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s_max_slice_ticks = g_settings.dma_max_slice_ticks;
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s_halt_ticks = g_settings.dma_halt_ticks;
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s_transfer_buffer.resize(32);
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s_unhalt_event =
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TimingEvents::CreateTimingEvent("DMA Transfer Unhalt", 1, s_max_slice_ticks, &DMA::UnhaltTransfer, nullptr, false);
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Reset();
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}
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void DMA::Shutdown()
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{
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ClearState();
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m_unhalt_event.reset();
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s_unhalt_event.reset();
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}
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void DMA::Reset()
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{
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ClearState();
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m_unhalt_event->Deactivate();
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s_unhalt_event->Deactivate();
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}
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void DMA::ClearState()
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{
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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ChannelState& cs = m_state[i];
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ChannelState& cs = s_state[i];
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cs.base_address = 0;
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cs.block_control.bits = 0;
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cs.channel_control.bits = 0;
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cs.request = false;
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}
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m_DPCR.bits = 0x07654321;
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m_DICR.bits = 0;
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s_DPCR.bits = 0x07654321;
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s_DICR.bits = 0;
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m_halt_ticks_remaining = 0;
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s_halt_ticks_remaining = 0;
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}
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bool DMA::DoState(StateWrapper& sw)
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{
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sw.Do(&m_halt_ticks_remaining);
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sw.Do(&s_halt_ticks_remaining);
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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ChannelState& cs = m_state[i];
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ChannelState& cs = s_state[i];
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sw.Do(&cs.base_address);
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sw.Do(&cs.block_control.bits);
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sw.Do(&cs.channel_control.bits);
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sw.Do(&cs.request);
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}
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sw.Do(&m_DPCR.bits);
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sw.Do(&m_DICR.bits);
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sw.Do(&s_DPCR.bits);
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sw.Do(&s_DICR.bits);
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if (sw.IsReading())
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{
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if (m_halt_ticks_remaining > 0)
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m_unhalt_event->SetIntervalAndSchedule(m_halt_ticks_remaining);
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if (s_halt_ticks_remaining > 0)
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s_unhalt_event->SetIntervalAndSchedule(s_halt_ticks_remaining);
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else
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m_unhalt_event->Deactivate();
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s_unhalt_event->Deactivate();
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}
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return !sw.HasError();
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@ -109,18 +264,18 @@ u32 DMA::ReadRegister(u32 offset)
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{
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case 0x00:
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{
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Log_TracePrintf("DMA%u base address -> 0x%08X", channel_index, m_state[channel_index].base_address);
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return m_state[channel_index].base_address;
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Log_TracePrintf("DMA%u base address -> 0x%08X", channel_index, s_state[channel_index].base_address);
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return s_state[channel_index].base_address;
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}
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case 0x04:
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{
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Log_TracePrintf("DMA%u block control -> 0x%08X", channel_index, m_state[channel_index].block_control.bits);
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return m_state[channel_index].block_control.bits;
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Log_TracePrintf("DMA%u block control -> 0x%08X", channel_index, s_state[channel_index].block_control.bits);
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return s_state[channel_index].block_control.bits;
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}
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case 0x08:
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{
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Log_TracePrintf("DMA%u channel control -> 0x%08X", channel_index, m_state[channel_index].channel_control.bits);
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return m_state[channel_index].channel_control.bits;
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Log_TracePrintf("DMA%u channel control -> 0x%08X", channel_index, s_state[channel_index].channel_control.bits);
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return s_state[channel_index].channel_control.bits;
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}
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default:
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break;
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@ -130,13 +285,13 @@ u32 DMA::ReadRegister(u32 offset)
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{
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if (offset == 0x70)
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{
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Log_TracePrintf("DPCR -> 0x%08X", m_DPCR.bits);
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return m_DPCR.bits;
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Log_TracePrintf("DPCR -> 0x%08X", s_DPCR.bits);
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return s_DPCR.bits;
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}
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else if (offset == 0x74)
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{
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Log_TracePrintf("DPCR -> 0x%08X", m_DPCR.bits);
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return m_DICR.bits;
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Log_TracePrintf("DPCR -> 0x%08X", s_DPCR.bits);
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return s_DICR.bits;
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}
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}
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@ -149,7 +304,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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const u32 channel_index = offset >> 4;
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if (channel_index < 7)
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{
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ChannelState& state = m_state[channel_index];
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ChannelState& state = s_state[channel_index];
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switch (offset & UINT32_C(0x0F))
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{
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case 0x00:
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@ -197,7 +352,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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case 0x70:
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{
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Log_TracePrintf("DPCR <- 0x%08X", value);
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m_DPCR.bits = value;
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s_DPCR.bits = value;
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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@ -214,9 +369,9 @@ void DMA::WriteRegister(u32 offset, u32 value)
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case 0x74:
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{
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Log_TracePrintf("DCIR <- 0x%08X", value);
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m_DICR.bits = (m_DICR.bits & ~DICR_WRITE_MASK) | (value & DICR_WRITE_MASK);
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m_DICR.bits = m_DICR.bits & ~(value & DICR_RESET_MASK);
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m_DICR.UpdateMasterFlag();
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s_DICR.bits = (s_DICR.bits & ~DICR_WRITE_MASK) | (value & DICR_WRITE_MASK);
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s_DICR.bits = s_DICR.bits & ~(value & DICR_RESET_MASK);
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s_DICR.UpdateMasterFlag();
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return;
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}
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@ -230,7 +385,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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void DMA::SetRequest(Channel channel, bool request)
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{
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ChannelState& cs = m_state[static_cast<u32>(channel)];
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ChannelState& cs = s_state[static_cast<u32>(channel)];
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if (cs.request == request)
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return;
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@ -239,12 +394,22 @@ void DMA::SetRequest(Channel channel, bool request)
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TransferChannel(channel);
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}
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bool DMA::CanTransferChannel(Channel channel, bool ignore_halt) const
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void DMA::SetMaxSliceTicks(TickCount ticks)
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{
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if (!m_DPCR.GetMasterEnable(channel))
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s_max_slice_ticks = ticks;
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}
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void DMA::SetHaltTicks(TickCount ticks)
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{
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s_halt_ticks = ticks;
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}
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bool DMA::CanTransferChannel(Channel channel, bool ignore_halt)
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{
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if (!s_DPCR.GetMasterEnable(channel))
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return false;
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const ChannelState& cs = m_state[static_cast<u32>(channel)];
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const ChannelState& cs = s_state[static_cast<u32>(channel)];
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if (!cs.channel_control.enable_busy)
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return false;
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@ -254,15 +419,15 @@ bool DMA::CanTransferChannel(Channel channel, bool ignore_halt) const
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return cs.request;
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}
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bool DMA::IsTransferHalted() const
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bool DMA::IsTransferHalted()
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{
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return m_unhalt_event->IsActive();
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return s_unhalt_event->IsActive();
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}
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void DMA::UpdateIRQ()
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{
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m_DICR.UpdateMasterFlag();
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if (m_DICR.master_flag)
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s_DICR.UpdateMasterFlag();
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if (s_DICR.master_flag)
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{
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Log_TracePrintf("Firing DMA master interrupt");
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g_interrupt_controller.InterruptRequest(InterruptController::IRQ::DMA);
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@ -279,27 +444,27 @@ enum : u32
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HALT_TICKS_WHEN_TRANSMITTING_PAD = 100
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};
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TickCount DMA::GetTransferSliceTicks() const
|
||||
TickCount DMA::GetTransferSliceTicks()
|
||||
{
|
||||
#ifdef _DEBUG
|
||||
if (g_pad.IsTransmitting())
|
||||
{
|
||||
Log_DebugPrintf("DMA transfer while transmitting pad - using lower slice size of %u vs %u",
|
||||
SLICE_SIZE_WHEN_TRANSMITTING_PAD, m_max_slice_ticks);
|
||||
SLICE_SIZE_WHEN_TRANSMITTING_PAD, s_max_slice_ticks);
|
||||
}
|
||||
#endif
|
||||
|
||||
return g_pad.IsTransmitting() ? SLICE_SIZE_WHEN_TRANSMITTING_PAD : m_max_slice_ticks;
|
||||
return g_pad.IsTransmitting() ? SLICE_SIZE_WHEN_TRANSMITTING_PAD : s_max_slice_ticks;
|
||||
}
|
||||
|
||||
TickCount DMA::GetTransferHaltTicks() const
|
||||
TickCount DMA::GetTransferHaltTicks()
|
||||
{
|
||||
return g_pad.IsTransmitting() ? HALT_TICKS_WHEN_TRANSMITTING_PAD : m_halt_ticks;
|
||||
return g_pad.IsTransmitting() ? HALT_TICKS_WHEN_TRANSMITTING_PAD : s_halt_ticks;
|
||||
}
|
||||
|
||||
bool DMA::TransferChannel(Channel channel)
|
||||
{
|
||||
ChannelState& cs = m_state[static_cast<u32>(channel)];
|
||||
ChannelState& cs = s_state[static_cast<u32>(channel)];
|
||||
const u32 mask = GetAddressMask();
|
||||
|
||||
const bool copy_to_device = cs.channel_control.copy_to_device;
|
||||
|
|
@ -433,7 +598,7 @@ bool DMA::TransferChannel(Channel channel)
|
|||
if (cs.request)
|
||||
{
|
||||
// we got halted
|
||||
if (!m_unhalt_event->IsActive())
|
||||
if (!s_unhalt_event->IsActive())
|
||||
HaltTransfer(GetTransferHaltTicks());
|
||||
|
||||
return false;
|
||||
|
|
@ -451,10 +616,10 @@ bool DMA::TransferChannel(Channel channel)
|
|||
|
||||
// start/busy bit is cleared on end of transfer
|
||||
cs.channel_control.enable_busy = false;
|
||||
if (m_DICR.IsIRQEnabled(channel))
|
||||
if (s_DICR.IsIRQEnabled(channel))
|
||||
{
|
||||
Log_DebugPrintf("Set DMA interrupt for channel %u", static_cast<u32>(channel));
|
||||
m_DICR.SetIRQFlag(channel);
|
||||
s_DICR.SetIRQFlag(channel);
|
||||
UpdateIRQ();
|
||||
}
|
||||
|
||||
|
|
@ -463,20 +628,20 @@ bool DMA::TransferChannel(Channel channel)
|
|||
|
||||
void DMA::HaltTransfer(TickCount duration)
|
||||
{
|
||||
m_halt_ticks_remaining += duration;
|
||||
Log_DebugPrintf("Halting DMA for %d ticks", m_halt_ticks_remaining);
|
||||
if (m_unhalt_event->IsActive())
|
||||
s_halt_ticks_remaining += duration;
|
||||
Log_DebugPrintf("Halting DMA for %d ticks", s_halt_ticks_remaining);
|
||||
if (s_unhalt_event->IsActive())
|
||||
return;
|
||||
|
||||
DebugAssert(!m_unhalt_event->IsActive());
|
||||
m_unhalt_event->SetIntervalAndSchedule(m_halt_ticks_remaining);
|
||||
DebugAssert(!s_unhalt_event->IsActive());
|
||||
s_unhalt_event->SetIntervalAndSchedule(s_halt_ticks_remaining);
|
||||
}
|
||||
|
||||
void DMA::UnhaltTransfer(TickCount ticks)
|
||||
void DMA::UnhaltTransfer(void*, TickCount ticks, TickCount ticks_late)
|
||||
{
|
||||
Log_DebugPrintf("Resuming DMA after %d ticks, %d ticks late", ticks, -(m_halt_ticks_remaining - ticks));
|
||||
m_halt_ticks_remaining -= ticks;
|
||||
m_unhalt_event->Deactivate();
|
||||
Log_DebugPrintf("Resuming DMA after %d ticks, %d ticks late", ticks, -(s_halt_ticks_remaining - ticks));
|
||||
s_halt_ticks_remaining -= ticks;
|
||||
s_unhalt_event->Deactivate();
|
||||
|
||||
// TODO: Use channel priority. But doing it in ascending order is probably good enough.
|
||||
// Main thing is that OTC happens after GPU, because otherwise it'll wipe out the LL.
|
||||
|
|
@ -490,7 +655,7 @@ void DMA::UnhaltTransfer(TickCount ticks)
|
|||
}
|
||||
|
||||
// We didn't run too long, so reset timer.
|
||||
m_halt_ticks_remaining = 0;
|
||||
s_halt_ticks_remaining = 0;
|
||||
}
|
||||
|
||||
TickCount DMA::TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u32 word_count)
|
||||
|
|
@ -501,14 +666,14 @@ TickCount DMA::TransferMemoryToDevice(Channel channel, u32 address, u32 incremen
|
|||
(static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & mask) <= address))
|
||||
{
|
||||
// Use temp buffer if it's wrapping around
|
||||
if (m_transfer_buffer.size() < word_count)
|
||||
m_transfer_buffer.resize(word_count);
|
||||
src_pointer = m_transfer_buffer.data();
|
||||
if (s_transfer_buffer.size() < word_count)
|
||||
s_transfer_buffer.resize(word_count);
|
||||
src_pointer = s_transfer_buffer.data();
|
||||
|
||||
u8* ram_pointer = Bus::g_ram;
|
||||
for (u32 i = 0; i < word_count; i++)
|
||||
{
|
||||
std::memcpy(&m_transfer_buffer[i], &ram_pointer[address], sizeof(u32));
|
||||
std::memcpy(&s_transfer_buffer[i], &ram_pointer[address], sizeof(u32));
|
||||
address = (address + increment) & mask;
|
||||
}
|
||||
}
|
||||
|
|
@ -577,9 +742,9 @@ TickCount DMA::TransferDeviceToMemory(Channel channel, u32 address, u32 incremen
|
|||
if (static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & mask) <= address)
|
||||
{
|
||||
// Use temp buffer if it's wrapping around
|
||||
if (m_transfer_buffer.size() < word_count)
|
||||
m_transfer_buffer.resize(word_count);
|
||||
dest_pointer = m_transfer_buffer.data();
|
||||
if (s_transfer_buffer.size() < word_count)
|
||||
s_transfer_buffer.resize(word_count);
|
||||
dest_pointer = s_transfer_buffer.data();
|
||||
}
|
||||
|
||||
// Read from device.
|
||||
|
|
@ -607,12 +772,12 @@ TickCount DMA::TransferDeviceToMemory(Channel channel, u32 address, u32 incremen
|
|||
break;
|
||||
}
|
||||
|
||||
if (dest_pointer == m_transfer_buffer.data())
|
||||
if (dest_pointer == s_transfer_buffer.data())
|
||||
{
|
||||
u8* ram_pointer = Bus::g_ram;
|
||||
for (u32 i = 0; i < word_count; i++)
|
||||
{
|
||||
std::memcpy(&ram_pointer[address], &m_transfer_buffer[i], sizeof(u32));
|
||||
std::memcpy(&ram_pointer[address], &s_transfer_buffer[i], sizeof(u32));
|
||||
address = (address + increment) & mask;
|
||||
}
|
||||
}
|
||||
|
|
@ -662,7 +827,7 @@ void DMA::DrawDebugStateWindow()
|
|||
|
||||
for (u32 i = 0; i < NUM_CHANNELS; i++)
|
||||
{
|
||||
const ChannelState& cs = m_state[i];
|
||||
const ChannelState& cs = s_state[i];
|
||||
|
||||
ImGui::TextColored(cs.channel_control.enable_busy ? active : inactive, "%u[%s]", i, channel_names[i]);
|
||||
ImGui::NextColumn();
|
||||
|
|
@ -682,17 +847,17 @@ void DMA::DrawDebugStateWindow()
|
|||
cs.channel_control.enable_busy ? "Busy" : "Idle",
|
||||
cs.channel_control.start_trigger ? " (Trigger)" : "");
|
||||
ImGui::NextColumn();
|
||||
ImGui::TextColored(m_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? active : inactive,
|
||||
m_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? "Enabled" : "Disabled");
|
||||
ImGui::TextColored(s_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? active : inactive,
|
||||
s_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? "Enabled" : "Disabled");
|
||||
ImGui::NextColumn();
|
||||
ImGui::TextColored(m_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? active : inactive, "%u",
|
||||
m_DPCR.GetPriority(static_cast<Channel>(i)));
|
||||
ImGui::TextColored(s_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? active : inactive, "%u",
|
||||
s_DPCR.GetPriority(static_cast<Channel>(i)));
|
||||
ImGui::NextColumn();
|
||||
ImGui::TextColored(m_DICR.IsIRQEnabled(static_cast<Channel>(i)) ? active : inactive,
|
||||
m_DICR.IsIRQEnabled(static_cast<Channel>(i)) ? "Enabled" : "Disabled");
|
||||
ImGui::TextColored(s_DICR.IsIRQEnabled(static_cast<Channel>(i)) ? active : inactive,
|
||||
s_DICR.IsIRQEnabled(static_cast<Channel>(i)) ? "Enabled" : "Disabled");
|
||||
ImGui::NextColumn();
|
||||
ImGui::TextColored(m_DICR.GetIRQFlag(static_cast<Channel>(i)) ? active : inactive,
|
||||
m_DICR.GetIRQFlag(static_cast<Channel>(i)) ? "IRQ" : "");
|
||||
ImGui::TextColored(s_DICR.GetIRQFlag(static_cast<Channel>(i)) ? active : inactive,
|
||||
s_DICR.GetIRQFlag(static_cast<Channel>(i)) ? "IRQ" : "");
|
||||
ImGui::NextColumn();
|
||||
}
|
||||
|
||||
|
|
|
|||
227
src/core/dma.h
227
src/core/dma.h
|
|
@ -2,207 +2,42 @@
|
|||
// SPDX-License-Identifier: (GPL-3.0 OR CC-BY-NC-ND-4.0)
|
||||
|
||||
#pragma once
|
||||
#include "common/bitfield.h"
|
||||
#include "types.h"
|
||||
#include <array>
|
||||
#include <memory>
|
||||
#include <vector>
|
||||
|
||||
class StateWrapper;
|
||||
|
||||
class TimingEvent;
|
||||
namespace DMA {
|
||||
|
||||
class DMA
|
||||
enum : u32
|
||||
{
|
||||
public:
|
||||
enum : u32
|
||||
{
|
||||
NUM_CHANNELS = 7
|
||||
};
|
||||
|
||||
enum class Channel : u32
|
||||
{
|
||||
MDECin = 0,
|
||||
MDECout = 1,
|
||||
GPU = 2,
|
||||
CDROM = 3,
|
||||
SPU = 4,
|
||||
PIO = 5,
|
||||
OTC = 6
|
||||
};
|
||||
|
||||
DMA();
|
||||
~DMA();
|
||||
|
||||
void Initialize();
|
||||
void Shutdown();
|
||||
void Reset();
|
||||
bool DoState(StateWrapper& sw);
|
||||
|
||||
u32 ReadRegister(u32 offset);
|
||||
void WriteRegister(u32 offset, u32 value);
|
||||
|
||||
void SetRequest(Channel channel, bool request);
|
||||
|
||||
// changing interfaces
|
||||
void SetMaxSliceTicks(TickCount ticks) { m_max_slice_ticks = ticks; }
|
||||
void SetHaltTicks(TickCount ticks) { m_halt_ticks = ticks; }
|
||||
|
||||
void DrawDebugStateWindow();
|
||||
|
||||
private:
|
||||
static constexpr PhysicalMemoryAddress BASE_ADDRESS_MASK = UINT32_C(0x00FFFFFF);
|
||||
static constexpr PhysicalMemoryAddress ADDRESS_MASK = UINT32_C(0x001FFFFC);
|
||||
|
||||
enum class SyncMode : u32
|
||||
{
|
||||
Manual = 0,
|
||||
Request = 1,
|
||||
LinkedList = 2,
|
||||
Reserved = 3
|
||||
};
|
||||
|
||||
void ClearState();
|
||||
|
||||
// is everything enabled for a channel to operate?
|
||||
bool CanTransferChannel(Channel channel, bool ignore_halt) const;
|
||||
bool IsTransferHalted() const;
|
||||
void UpdateIRQ();
|
||||
|
||||
// returns false if the DMA should now be halted
|
||||
TickCount GetTransferSliceTicks() const;
|
||||
TickCount GetTransferHaltTicks() const;
|
||||
bool TransferChannel(Channel channel);
|
||||
void HaltTransfer(TickCount duration);
|
||||
void UnhaltTransfer(TickCount ticks);
|
||||
|
||||
// from device -> memory
|
||||
TickCount TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u32 word_count);
|
||||
|
||||
// from memory -> device
|
||||
TickCount TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u32 word_count);
|
||||
|
||||
// configuration
|
||||
TickCount m_max_slice_ticks = 1000;
|
||||
TickCount m_halt_ticks = 100;
|
||||
|
||||
std::vector<u32> m_transfer_buffer;
|
||||
std::unique_ptr<TimingEvent> m_unhalt_event;
|
||||
TickCount m_halt_ticks_remaining = 0;
|
||||
|
||||
struct ChannelState
|
||||
{
|
||||
u32 base_address = 0;
|
||||
|
||||
union BlockControl
|
||||
{
|
||||
u32 bits;
|
||||
union
|
||||
{
|
||||
BitField<u32, u32, 0, 16> word_count;
|
||||
|
||||
u32 GetWordCount() const { return (word_count == 0) ? 0x10000 : word_count; }
|
||||
} manual;
|
||||
union
|
||||
{
|
||||
BitField<u32, u32, 0, 16> block_size;
|
||||
BitField<u32, u32, 16, 16> block_count;
|
||||
|
||||
u32 GetBlockSize() const { return (block_size == 0) ? 0x10000 : block_size; }
|
||||
u32 GetBlockCount() const { return (block_count == 0) ? 0x10000 : block_count; }
|
||||
} request;
|
||||
} block_control = {};
|
||||
|
||||
union ChannelControl
|
||||
{
|
||||
u32 bits;
|
||||
BitField<u32, bool, 0, 1> copy_to_device;
|
||||
BitField<u32, bool, 1, 1> address_step_reverse;
|
||||
BitField<u32, bool, 8, 1> chopping_enable;
|
||||
BitField<u32, SyncMode, 9, 2> sync_mode;
|
||||
BitField<u32, u32, 16, 3> chopping_dma_window_size;
|
||||
BitField<u32, u32, 20, 3> chopping_cpu_window_size;
|
||||
BitField<u32, bool, 24, 1> enable_busy;
|
||||
BitField<u32, bool, 28, 1> start_trigger;
|
||||
|
||||
static constexpr u32 WRITE_MASK = 0b01110001'01110111'00000111'00000011;
|
||||
} channel_control = {};
|
||||
|
||||
bool request = false;
|
||||
};
|
||||
|
||||
std::array<ChannelState, NUM_CHANNELS> m_state;
|
||||
|
||||
union DPCR
|
||||
{
|
||||
u32 bits;
|
||||
|
||||
BitField<u32, u8, 0, 3> MDECin_priority;
|
||||
BitField<u32, bool, 3, 1> MDECin_master_enable;
|
||||
BitField<u32, u8, 4, 3> MDECout_priority;
|
||||
BitField<u32, bool, 7, 1> MDECout_master_enable;
|
||||
BitField<u32, u8, 8, 3> GPU_priority;
|
||||
BitField<u32, bool, 10, 1> GPU_master_enable;
|
||||
BitField<u32, u8, 12, 3> CDROM_priority;
|
||||
BitField<u32, bool, 15, 1> CDROM_master_enable;
|
||||
BitField<u32, u8, 16, 3> SPU_priority;
|
||||
BitField<u32, bool, 19, 1> SPU_master_enable;
|
||||
BitField<u32, u8, 20, 3> PIO_priority;
|
||||
BitField<u32, bool, 23, 1> PIO_master_enable;
|
||||
BitField<u32, u8, 24, 3> OTC_priority;
|
||||
BitField<u32, bool, 27, 1> OTC_master_enable;
|
||||
BitField<u32, u8, 28, 3> priority_offset;
|
||||
BitField<u32, bool, 31, 1> unused;
|
||||
|
||||
u8 GetPriority(Channel channel) const { return ((bits >> (static_cast<u8>(channel) * 4)) & u32(3)); }
|
||||
bool GetMasterEnable(Channel channel) const
|
||||
{
|
||||
return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) * 4 + 3)) & u32(1));
|
||||
}
|
||||
} m_DPCR = {};
|
||||
|
||||
static constexpr u32 DICR_WRITE_MASK = 0b00000000'11111111'10000000'00111111;
|
||||
static constexpr u32 DICR_RESET_MASK = 0b01111111'00000000'00000000'00000000;
|
||||
union DICR
|
||||
{
|
||||
u32 bits;
|
||||
|
||||
BitField<u32, bool, 15, 1> force_irq;
|
||||
BitField<u32, bool, 16, 1> MDECin_irq_enable;
|
||||
BitField<u32, bool, 17, 1> MDECout_irq_enable;
|
||||
BitField<u32, bool, 18, 1> GPU_irq_enable;
|
||||
BitField<u32, bool, 19, 1> CDROM_irq_enable;
|
||||
BitField<u32, bool, 20, 1> SPU_irq_enable;
|
||||
BitField<u32, bool, 21, 1> PIO_irq_enable;
|
||||
BitField<u32, bool, 22, 1> OTC_irq_enable;
|
||||
BitField<u32, bool, 23, 1> master_enable;
|
||||
BitField<u32, bool, 24, 1> MDECin_irq_flag;
|
||||
BitField<u32, bool, 25, 1> MDECout_irq_flag;
|
||||
BitField<u32, bool, 26, 1> GPU_irq_flag;
|
||||
BitField<u32, bool, 27, 1> CDROM_irq_flag;
|
||||
BitField<u32, bool, 28, 1> SPU_irq_flag;
|
||||
BitField<u32, bool, 29, 1> PIO_irq_flag;
|
||||
BitField<u32, bool, 30, 1> OTC_irq_flag;
|
||||
BitField<u32, bool, 31, 1> master_flag;
|
||||
|
||||
bool IsIRQEnabled(Channel channel) const
|
||||
{
|
||||
return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 16)) & u32(1));
|
||||
}
|
||||
|
||||
bool GetIRQFlag(Channel channel) const
|
||||
{
|
||||
return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 24)) & u32(1));
|
||||
}
|
||||
|
||||
void SetIRQFlag(Channel channel) { bits |= (u32(1) << (static_cast<u8>(channel) + 24)); }
|
||||
void ClearIRQFlag(Channel channel) { bits &= ~(u32(1) << (static_cast<u8>(channel) + 24)); }
|
||||
|
||||
void UpdateMasterFlag()
|
||||
{
|
||||
master_flag = master_enable && ((((bits >> 16) & u32(0b1111111)) & ((bits >> 24) & u32(0b1111111))) != 0);
|
||||
}
|
||||
} m_DICR = {};
|
||||
NUM_CHANNELS = 7
|
||||
};
|
||||
|
||||
extern DMA g_dma;
|
||||
enum class Channel : u32
|
||||
{
|
||||
MDECin = 0,
|
||||
MDECout = 1,
|
||||
GPU = 2,
|
||||
CDROM = 3,
|
||||
SPU = 4,
|
||||
PIO = 5,
|
||||
OTC = 6
|
||||
};
|
||||
|
||||
void Initialize();
|
||||
void Shutdown();
|
||||
void Reset();
|
||||
bool DoState(StateWrapper& sw);
|
||||
|
||||
u32 ReadRegister(u32 offset);
|
||||
void WriteRegister(u32 offset, u32 value);
|
||||
|
||||
void SetRequest(Channel channel, bool request);
|
||||
|
||||
// changing interfaces
|
||||
void SetMaxSliceTicks(TickCount ticks);
|
||||
void SetHaltTicks(TickCount ticks);
|
||||
|
||||
void DrawDebugStateWindow();
|
||||
|
||||
} // namespace DMA
|
||||
|
|
|
|||
|
|
@ -341,7 +341,7 @@ void GPU::UpdateDMARequest()
|
|||
break;
|
||||
}
|
||||
m_GPUSTAT.dma_data_request = dma_request;
|
||||
g_dma.SetRequest(DMA::Channel::GPU, dma_request);
|
||||
DMA::SetRequest(DMA::Channel::GPU, dma_request);
|
||||
}
|
||||
|
||||
void GPU::UpdateGPUIdle()
|
||||
|
|
|
|||
|
|
@ -307,12 +307,12 @@ void MDEC::UpdateStatus()
|
|||
// we always want data in if it's enabled
|
||||
const bool data_in_request = s_enable_dma_in && s_data_in_fifo.GetSpace() >= (32 * 2);
|
||||
s_status.data_in_request = data_in_request;
|
||||
g_dma.SetRequest(DMA::Channel::MDECin, data_in_request);
|
||||
DMA::SetRequest(DMA::Channel::MDECin, data_in_request);
|
||||
|
||||
// we only want to send data out if we have some in the fifo
|
||||
const bool data_out_request = s_enable_dma_out && !s_data_out_fifo.IsEmpty();
|
||||
s_status.data_out_request = data_out_request;
|
||||
g_dma.SetRequest(DMA::Channel::MDECout, data_out_request);
|
||||
DMA::SetRequest(DMA::Channel::MDECout, data_out_request);
|
||||
}
|
||||
|
||||
u32 MDEC::ReadDataRegister()
|
||||
|
|
|
|||
|
|
@ -1349,7 +1349,7 @@ void SPU::UpdateDMARequest()
|
|||
}
|
||||
|
||||
// This might call us back directly.
|
||||
g_dma.SetRequest(DMA::Channel::SPU, s_SPUSTAT.dma_request);
|
||||
DMA::SetRequest(DMA::Channel::SPU, s_SPUSTAT.dma_request);
|
||||
}
|
||||
|
||||
void SPU::DMARead(u32* words, u32 word_count)
|
||||
|
|
|
|||
|
|
@ -1386,7 +1386,7 @@ bool System::Initialize(bool force_software_renderer)
|
|||
// CPU code cache must happen after GPU, because it might steal our address space.
|
||||
CPU::CodeCache::Initialize();
|
||||
|
||||
g_dma.Initialize();
|
||||
DMA::Initialize();
|
||||
g_interrupt_controller.Initialize();
|
||||
|
||||
CDROM::Initialize();
|
||||
|
|
@ -1458,7 +1458,7 @@ void System::DestroySystem()
|
|||
CDROM::Shutdown();
|
||||
g_gpu.reset();
|
||||
g_interrupt_controller.Shutdown();
|
||||
g_dma.Shutdown();
|
||||
DMA::Shutdown();
|
||||
PGXP::Shutdown();
|
||||
CPU::CodeCache::Shutdown();
|
||||
Bus::Shutdown();
|
||||
|
|
@ -1640,7 +1640,7 @@ bool System::DoState(StateWrapper& sw, GPUTexture** host_texture, bool update_di
|
|||
if (!sw.DoMarker("Bus") || !Bus::DoState(sw))
|
||||
return false;
|
||||
|
||||
if (!sw.DoMarker("DMA") || !g_dma.DoState(sw))
|
||||
if (!sw.DoMarker("DMA") || !DMA::DoState(sw))
|
||||
return false;
|
||||
|
||||
if (!sw.DoMarker("InterruptController") || !g_interrupt_controller.DoState(sw))
|
||||
|
|
@ -1739,7 +1739,7 @@ void System::InternalReset()
|
|||
PGXP::Initialize();
|
||||
|
||||
Bus::Reset();
|
||||
g_dma.Reset();
|
||||
DMA::Reset();
|
||||
g_interrupt_controller.Reset();
|
||||
g_gpu->Reset(true);
|
||||
CDROM::Reset();
|
||||
|
|
@ -3299,8 +3299,8 @@ void System::CheckForSettingsChanges(const Settings& old_settings)
|
|||
g_texture_replacements.Reload();
|
||||
}
|
||||
|
||||
g_dma.SetMaxSliceTicks(g_settings.dma_max_slice_ticks);
|
||||
g_dma.SetHaltTicks(g_settings.dma_halt_ticks);
|
||||
DMA::SetMaxSliceTicks(g_settings.dma_max_slice_ticks);
|
||||
DMA::SetHaltTicks(g_settings.dma_halt_ticks);
|
||||
|
||||
if (g_settings.audio_backend != old_settings.audio_backend ||
|
||||
g_settings.video_sync_enabled != old_settings.video_sync_enabled ||
|
||||
|
|
|
|||
|
|
@ -490,7 +490,7 @@ void ImGuiManager::RenderDebugWindows()
|
|||
if (g_settings.debugging.show_mdec_state)
|
||||
MDEC::DrawDebugStateWindow();
|
||||
if (g_settings.debugging.show_dma_state)
|
||||
g_dma.DrawDebugStateWindow();
|
||||
DMA::DrawDebugStateWindow();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue