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SPU: Handle IRQ address register (fixes FF8 intro FMV)

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This commit is contained in:
Connor McLaughlin 2019-10-23 00:50:00 +10:00
parent c048679044
commit 3db77a3139
1 changed files with 41 additions and 30 deletions
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71
src/core/spu.cpp
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@ -147,6 +147,10 @@ u16 SPU::ReadRegister(u32 offset)
case 0x1F801D9A - SPU_BASE: case 0x1F801D9A - SPU_BASE:
return Truncate16(m_reverb_on_register >> 16); return Truncate16(m_reverb_on_register >> 16);
case 0x1F801DA4 - SPU_BASE:
Log_DebugPrintf("SPU IRQ address -> 0x%04X", ZeroExtend32(m_irq_address));
return m_irq_address;
case 0x1F801DA6 - SPU_BASE: case 0x1F801DA6 - SPU_BASE:
Log_DebugPrintf("SPU transfer address register -> 0x%04X", ZeroExtend32(m_transfer_address_reg)); Log_DebugPrintf("SPU transfer address register -> 0x%04X", ZeroExtend32(m_transfer_address_reg));
return m_transfer_address_reg; return m_transfer_address_reg;
@ -185,36 +189,6 @@ void SPU::WriteRegister(u32 offset, u16 value)
switch (offset) switch (offset)
{ {
case 0x1F801DA6 - SPU_BASE:
{
Log_DebugPrintf("SPU transfer address register <- 0x%04X", ZeroExtend32(value));
m_transfer_address_reg = value;
m_transfer_address = (ZeroExtend32(value) << VOICE_ADDRESS_SHIFT) & RAM_MASK;
return;
}
case 0x1F801DA8 - SPU_BASE:
{
Log_TracePrintf("SPU transfer data register <- 0x%04X (RAM offset 0x%08X)", ZeroExtend32(value),
m_transfer_address);
RAMTransferWrite(value);
return;
}
case 0x1F801DAA - SPU_BASE:
{
Log_DebugPrintf("SPU control register <- 0x%04X", ZeroExtend32(value));
m_SPUCNT.bits = value;
m_SPUSTAT.mode = m_SPUCNT.mode.GetValue();
m_SPUSTAT.dma_read_write_request = m_SPUCNT.ram_transfer_mode >= RAMTransferMode::DMAWrite;
if (!m_SPUCNT.irq9_enable)
m_SPUSTAT.irq9_flag = false;
UpdateDMARequest();
return;
}
case 0x1F801D80 - SPU_BASE: case 0x1F801D80 - SPU_BASE:
{ {
Log_DebugPrintf("SPU main volume left <- 0x%04X", ZeroExtend32(value)); Log_DebugPrintf("SPU main volume left <- 0x%04X", ZeroExtend32(value));
@ -339,6 +313,43 @@ void SPU::WriteRegister(u32 offset, u16 value)
} }
break; break;
case 0x1F801DA4 - SPU_BASE:
{
Log_DebugPrintf("SPU IRQ address register <- 0x%04X", ZeroExtend32(value));
m_irq_address = value;
return;
}
case 0x1F801DA6 - SPU_BASE:
{
Log_DebugPrintf("SPU transfer address register <- 0x%04X", ZeroExtend32(value));
m_transfer_address_reg = value;
m_transfer_address = (ZeroExtend32(value) << VOICE_ADDRESS_SHIFT) & RAM_MASK;
return;
}
case 0x1F801DA8 - SPU_BASE:
{
Log_TracePrintf("SPU transfer data register <- 0x%04X (RAM offset 0x%08X)", ZeroExtend32(value),
m_transfer_address);
RAMTransferWrite(value);
return;
}
case 0x1F801DAA - SPU_BASE:
{
Log_DebugPrintf("SPU control register <- 0x%04X", ZeroExtend32(value));
m_SPUCNT.bits = value;
m_SPUSTAT.mode = m_SPUCNT.mode.GetValue();
m_SPUSTAT.dma_read_write_request = m_SPUCNT.ram_transfer_mode >= RAMTransferMode::DMAWrite;
if (!m_SPUCNT.irq9_enable)
m_SPUSTAT.irq9_flag = false;
UpdateDMARequest();
return;
}
case 0x1F801DB0 - SPU_BASE: case 0x1F801DB0 - SPU_BASE:
{ {
Log_DebugPrintf("SPU left cd audio register <- 0x%04X", ZeroExtend32(value)); Log_DebugPrintf("SPU left cd audio register <- 0x%04X", ZeroExtend32(value));