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CPU: Silence some debug spam
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parent
6aa36c2ead
commit
4aca52cdf4
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@ -82,8 +82,8 @@ static int Run(int argc, char* argv[])
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int main(int argc, char* argv[])
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int main(int argc, char* argv[])
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{
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{
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// set log flags
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// set log flags
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g_pLog->SetConsoleOutputParams(true, nullptr, LOGLEVEL_DEBUG);
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// g_pLog->SetConsoleOutputParams(true, nullptr, LOGLEVEL_DEBUG);
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// g_pLog->SetConsoleOutputParams(true, "GPU GPU_HW_OpenGL DMA Pad DigitalController", LOGLEVEL_DEBUG);
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g_pLog->SetConsoleOutputParams(true, "GPU GPU_HW_OpenGL SPU Pad DigitalController", LOGLEVEL_DEBUG);
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#ifdef Y_BUILD_CONFIG_RELEASE
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#ifdef Y_BUILD_CONFIG_RELEASE
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g_pLog->SetFilterLevel(LOGLEVEL_INFO);
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g_pLog->SetFilterLevel(LOGLEVEL_INFO);
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@ -376,7 +376,7 @@ void Core::WriteCop0Reg(Cop0Reg reg, u32 value)
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{
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{
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m_cop0_regs.sr.bits =
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m_cop0_regs.sr.bits =
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(m_cop0_regs.sr.bits & ~Cop0Registers::SR::WRITE_MASK) | (value & Cop0Registers::SR::WRITE_MASK);
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(m_cop0_regs.sr.bits & ~Cop0Registers::SR::WRITE_MASK) | (value & Cop0Registers::SR::WRITE_MASK);
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Log_WarningPrintf("COP0 SR <- %08X (now %08X)", value, m_cop0_regs.sr.bits);
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Log_DebugPrintf("COP0 SR <- %08X (now %08X)", value, m_cop0_regs.sr.bits);
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}
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}
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break;
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break;
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@ -384,7 +384,7 @@ void Core::WriteCop0Reg(Cop0Reg reg, u32 value)
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{
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{
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m_cop0_regs.cause.bits =
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m_cop0_regs.cause.bits =
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(m_cop0_regs.cause.bits & ~Cop0Registers::CAUSE::WRITE_MASK) | (value & Cop0Registers::CAUSE::WRITE_MASK);
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(m_cop0_regs.cause.bits & ~Cop0Registers::CAUSE::WRITE_MASK) | (value & Cop0Registers::CAUSE::WRITE_MASK);
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Log_WarningPrintf("COP0 CAUSE <- %08X (now %08X)", value, m_cop0_regs.cause.bits);
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Log_DebugPrintf("COP0 CAUSE <- %08X (now %08X)", value, m_cop0_regs.cause.bits);
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}
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}
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break;
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break;
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