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https://github.com/RetroDECK/Duckstation.git
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CPU: Refactor load delay handling
Now works when mixing interpreter and recompiler code.
This commit is contained in:
Connor McLaughlin
parent
1d6c4a3af1
commit
5217088d82
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@ -4,6 +4,9 @@
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#include "cpu_disasm.h"
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#include "cpu_recompiler_code_generator.h"
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#include "cpu_recompiler_thunks.h"
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#include "system.h"
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#include <thread>
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#include <chrono>
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Log_SetChannel(CPU::CodeCache);
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namespace CPU {
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@ -15,8 +18,9 @@ CodeCache::CodeCache() = default;
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CodeCache::~CodeCache() = default;
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void CodeCache::Initialize(Core* core, Bus* bus)
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void CodeCache::Initialize(System* system, Core* core, Bus* bus)
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{
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m_system = system;
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m_core = core;
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m_bus = bus;
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@ -122,9 +126,12 @@ bool CodeCache::CompileBlock(CodeBlock* block)
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}
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cbi.pc = pc;
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cbi.is_branch = IsBranchInstruction(cbi.instruction);
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cbi.is_branch_delay_slot = is_branch_delay_slot;
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cbi.is_load_delay_slot = is_load_delay_slot;
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cbi.is_branch_instruction = IsBranchInstruction(cbi.instruction);
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cbi.is_load_instruction = IsMemoryLoadInstruction(cbi.instruction);
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cbi.is_store_instruction = IsMemoryStoreInstruction(cbi.instruction);
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cbi.has_load_delay = InstructionHasLoadDelay(cbi.instruction);
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cbi.can_trap = CanInstructionTrap(cbi.instruction, m_core->InUserMode());
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// instruction is decoded now
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@ -133,11 +140,14 @@ bool CodeCache::CompileBlock(CodeBlock* block)
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// if we're in a branch delay slot, the block is now done
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// except if this is a branch in a branch delay slot, then we grab the one after that, and so on...
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if (is_branch_delay_slot && !cbi.is_branch)
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if (is_branch_delay_slot && !cbi.is_branch_instruction)
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break;
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// if this is a branch, we grab the next instruction (delay slot), and then exit
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is_branch_delay_slot = cbi.is_branch;
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is_branch_delay_slot = cbi.is_branch_instruction;
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// same for load delay
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is_load_delay_slot = cbi.has_load_delay;
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// is this a non-branchy exit? (e.g. syscall)
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if (IsExitBlockInstruction(cbi.instruction))
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@ -254,10 +264,7 @@ void CodeCache::InterpretCachedBlock(const CodeBlock& block)
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m_core->ExecuteInstruction();
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// next load delay
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m_core->m_load_delay_reg = m_core->m_next_load_delay_reg;
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m_core->m_next_load_delay_reg = Reg::count;
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m_core->m_load_delay_old_value = m_core->m_next_load_delay_old_value;
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m_core->m_next_load_delay_old_value = 0;
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m_core->UpdateLoadDelay();
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if (m_core->m_exception_raised)
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break;
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@ -294,10 +301,7 @@ void CodeCache::InterpretUncachedBlock()
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m_core->ExecuteInstruction();
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// next load delay
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m_core->m_load_delay_reg = m_core->m_next_load_delay_reg;
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m_core->m_next_load_delay_reg = Reg::count;
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m_core->m_load_delay_old_value = m_core->m_next_load_delay_old_value;
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m_core->m_next_load_delay_old_value = 0;
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m_core->UpdateLoadDelay();
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const bool branch = IsBranchInstruction(m_core->m_current_instruction);
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if (m_core->m_exception_raised || (!branch && in_branch_delay_slot) ||
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@ -9,6 +9,7 @@
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class JitCodeBuffer;
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class Bus;
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class System;
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namespace CPU {
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class Core;
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@ -23,7 +24,7 @@ public:
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CodeCache();
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~CodeCache();
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void Initialize(Core* core, Bus* bus);
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void Initialize(System* system, Core* core, Bus* bus);
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void Reset();
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void Execute();
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@ -39,6 +40,7 @@ private:
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void InterpretCachedBlock(const CodeBlock& block);
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void InterpretUncachedBlock();
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System* m_system;
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Core* m_core;
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Bus* m_bus;
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@ -97,8 +97,10 @@ bool Core::DoState(StateWrapper& sw)
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sw.Do(&m_next_instruction_is_branch_delay_slot);
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sw.Do(&m_branch_was_taken);
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sw.Do(&m_load_delay_reg);
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sw.Do(&m_load_delay_value);
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sw.Do(&m_load_delay_old_value);
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sw.Do(&m_next_load_delay_reg);
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sw.Do(&m_next_load_delay_value);
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sw.Do(&m_next_load_delay_old_value);
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sw.Do(&m_cache_control);
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sw.DoBytes(m_dcache.data(), m_dcache.size());
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@ -338,7 +340,7 @@ bool Core::HasPendingInterrupt()
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// const bool do_interrupt = m_cop0_regs.sr.IEc && ((m_cop0_regs.cause.Ip & m_cop0_regs.sr.Im) != 0);
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const bool do_interrupt =
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m_cop0_regs.sr.IEc && (((m_cop0_regs.cause.bits & m_cop0_regs.sr.bits) & (UINT32_C(0xFF) << 8)) != 0);
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return do_interrupt;
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}
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@ -354,19 +356,16 @@ void Core::DispatchInterrupt()
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m_next_instruction.cop.cop_n);
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}
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void Core::FlushLoadDelay()
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{
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m_load_delay_reg = Reg::count;
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m_load_delay_old_value = 0;
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m_next_load_delay_reg = Reg::count;
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m_next_load_delay_old_value = 0;
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}
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void Core::FlushPipeline()
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{
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// loads are flushed
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FlushLoadDelay();
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m_next_load_delay_reg = Reg::count;
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if (m_load_delay_reg != Reg::count)
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{
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m_regs.r[static_cast<u8>(m_load_delay_reg)] = m_load_delay_value;
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m_load_delay_reg = Reg::count;
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}
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// not in a branch delay slot
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m_branch_was_taken = false;
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m_next_instruction_is_branch_delay_slot = false;
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@ -383,13 +382,15 @@ void Core::FlushPipeline()
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u32 Core::ReadReg(Reg rs)
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{
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return rs == m_load_delay_reg ? m_load_delay_old_value : m_regs.r[static_cast<u8>(rs)];
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return m_regs.r[static_cast<u8>(rs)];
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}
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void Core::WriteReg(Reg rd, u32 value)
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{
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if (rd != Reg::zero)
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m_regs.r[static_cast<u8>(rd)] = value;
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m_regs.r[static_cast<u8>(rd)] = value;
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// prevent writes to $zero from going through - better than branching/cmov
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m_regs.zero = 0;
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}
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void Core::WriteRegDelayed(Reg rd, u32 value)
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@ -398,10 +399,14 @@ void Core::WriteRegDelayed(Reg rd, u32 value)
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if (rd == Reg::zero)
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return;
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// save the old value, this will be returned if the register is read in the next instruction
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// double load delays ignore the first value
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if (m_load_delay_reg == rd)
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m_load_delay_reg = Reg::count;
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// save the old value, if something else overwrites this reg we want to preserve it
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m_next_load_delay_reg = rd;
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m_next_load_delay_old_value = ReadReg(rd);
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m_regs.r[static_cast<u8>(rd)] = value;
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m_next_load_delay_value = value;
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m_next_load_delay_old_value = m_regs.r[static_cast<u8>(rd)];
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}
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std::optional<u32> Core::ReadCop0Reg(Cop0Reg reg)
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@ -608,10 +613,7 @@ void Core::Execute()
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ExecuteInstruction();
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// next load delay
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m_load_delay_reg = m_next_load_delay_reg;
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m_next_load_delay_reg = Reg::count;
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m_load_delay_old_value = m_next_load_delay_old_value;
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m_next_load_delay_old_value = 0;
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UpdateLoadDelay();
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}
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}
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@ -643,12 +645,12 @@ void Core::ExecuteInstruction()
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}
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#endif
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//#ifdef _DEBUG
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//#ifdef _DEBUG
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if (TRACE_EXECUTION)
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PrintInstruction(inst.bits, m_current_instruction_pc, this);
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if (LOG_EXECUTION)
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LogInstruction(inst.bits, m_current_instruction_pc, this);
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//#endif
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//#endif
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switch (inst.op)
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{
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@ -1039,8 +1041,8 @@ void Core::ExecuteInstruction()
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if (!ReadMemoryWord(aligned_addr, &aligned_value))
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return;
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// note: bypasses load delay on the read
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const u32 existing_value = m_regs.r[static_cast<u8>(inst.i.rt.GetValue())];
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// Bypasses load delay. No need to check the old value since this is the delay slot or it's not relevant.
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const u32 existing_value = (inst.i.rt == m_load_delay_reg) ? m_load_delay_value : ReadReg(inst.i.rt);
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const u8 shift = (Truncate8(addr) & u8(3)) * u8(8);
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u32 new_value;
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if (inst.op == InstructionOp::lwl)
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@ -14,11 +14,10 @@ namespace CPU {
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class CodeCache;
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namespace Recompiler
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{
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namespace Recompiler {
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class CodeGenerator;
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class Thunks;
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}
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} // namespace Recompiler
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class Core
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{
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@ -28,7 +27,7 @@ public:
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static constexpr PhysicalMemoryAddress DCACHE_LOCATION_MASK = UINT32_C(0xFFFFFC00);
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static constexpr PhysicalMemoryAddress DCACHE_OFFSET_MASK = UINT32_C(0x000003FF);
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static constexpr PhysicalMemoryAddress DCACHE_SIZE = UINT32_C(0x00000400);
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friend CodeCache;
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friend Recompiler::CodeGenerator;
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friend Recompiler::Thunks;
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@ -103,6 +102,19 @@ private:
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void DisassembleAndLog(u32 addr);
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void DisassembleAndPrint(u32 addr, u32 instructions_before, u32 instructions_after);
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// Updates load delays - call after each instruction
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ALWAYS_INLINE void UpdateLoadDelay()
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{
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// the old value is needed in case the delay slot instruction overwrites the same register
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if (m_load_delay_reg != Reg::count && m_regs.r[static_cast<u8>(m_load_delay_reg)] == m_load_delay_old_value)
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m_regs.r[static_cast<u8>(m_load_delay_reg)] = m_load_delay_value;
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m_load_delay_reg = m_next_load_delay_reg;
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m_load_delay_value = m_next_load_delay_value;
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m_load_delay_old_value = m_next_load_delay_old_value;
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m_next_load_delay_reg = Reg::count;
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}
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// Fetches the instruction at m_regs.npc
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bool FetchInstruction();
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void ExecuteInstruction();
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@ -117,9 +129,6 @@ private:
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bool HasPendingInterrupt();
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void DispatchInterrupt();
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// flushes any load delays if present
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void FlushLoadDelay();
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// clears pipeline of load/branch delays
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void FlushPipeline();
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@ -158,8 +167,10 @@ private:
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// load delays
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Reg m_load_delay_reg = Reg::count;
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u32 m_load_delay_value = 0;
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u32 m_load_delay_old_value = 0;
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Reg m_next_load_delay_reg = Reg::count;
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u32 m_next_load_delay_value = 0;
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u32 m_next_load_delay_old_value = 0;
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u32 m_cache_control = 0;
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@ -28,11 +28,6 @@ bool CodeGenerator::CompileBlock(const CodeBlock* block, CodeBlock::HostCodePoin
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m_block_start = block->instructions.data();
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m_block_end = block->instructions.data() + block->instructions.size();
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m_current_instruction_in_branch_delay_slot_dirty = true;
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m_branch_was_taken_dirty = true;
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m_current_instruction_was_branch_taken_dirty = false;
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m_load_delay_dirty = true;
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EmitBeginBlock();
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BlockPrologue();
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@ -340,7 +335,11 @@ void CodeGenerator::BlockPrologue()
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{
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EmitStoreCPUStructField(offsetof(Core, m_exception_raised), Value::FromConstantU8(0));
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// fetching of the first instruction...
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// we don't know the state of the last block, so assume load delays might be in progress
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m_current_instruction_in_branch_delay_slot_dirty = true;
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m_branch_was_taken_dirty = true;
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m_current_instruction_was_branch_taken_dirty = false;
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m_load_delay_dirty = true;
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// sync m_current_instruction_pc so we can simply add to it
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SyncCurrentInstructionPC();
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@ -435,7 +434,7 @@ void CodeGenerator::InstructionPrologue(const CodeBlockInstruction& cbi, TickCou
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m_delayed_pc_add = 0;
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}
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if (!cbi.is_branch)
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if (!cbi.is_branch_instruction)
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m_delayed_pc_add = INSTRUCTION_SIZE;
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m_delayed_cycles_add += cycles;
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@ -445,38 +444,18 @@ void CodeGenerator::InstructionPrologue(const CodeBlockInstruction& cbi, TickCou
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void CodeGenerator::InstructionEpilogue(const CodeBlockInstruction& cbi)
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{
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// copy if the previous instruction was a load, reset the current value on the next instruction
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if (m_load_delay_dirty)
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if (m_next_load_delay_dirty)
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{
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// cpu->m_load_delay_reg = cpu->m_next_load_delay_reg;
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// cpu->m_next_load_delay_reg = Reg::count;
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{
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Value temp = m_register_cache.AllocateScratch(RegSize_8);
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EmitLoadCPUStructField(temp.host_reg, RegSize_8, offsetof(Core, m_next_load_delay_reg));
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EmitStoreCPUStructField(offsetof(Core, m_next_load_delay_reg),
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Value::FromConstantU8(static_cast<u8>(Reg::count)));
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EmitStoreCPUStructField(offsetof(Core, m_load_delay_reg), temp);
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}
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// cpu->m_load_delay_old_value = cpu->m_next_load_delay_old_value;
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// cpu->m_next_load_delay_old_value = 0;
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{
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Value temp = m_register_cache.AllocateScratch(RegSize_32);
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EmitLoadCPUStructField(temp.host_reg, RegSize_32, offsetof(Core, m_next_load_delay_old_value));
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EmitStoreCPUStructField(offsetof(Core, m_next_load_delay_old_value), Value::FromConstantU32(0));
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EmitStoreCPUStructField(offsetof(Core, m_load_delay_old_value), temp);
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}
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m_load_delay_dirty = false;
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m_next_load_delay_dirty = true;
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}
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else if (m_next_load_delay_dirty)
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{
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// cpu->m_load_delay_reg = Reg::count;
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// cpu->m_load_delay_old_value = 0;
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EmitStoreCPUStructField(offsetof(Core, m_load_delay_reg), Value::FromConstantU8(static_cast<u8>(Reg::count)));
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EmitStoreCPUStructField(offsetof(Core, m_load_delay_old_value), Value::FromConstantU32(0));
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Log_DebugPrint("Emitting delay slot flush (with move next)");
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EmitDelaySlotUpdate(false, false, true);
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m_next_load_delay_dirty = false;
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m_load_delay_dirty = true;
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}
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else if (m_load_delay_dirty)
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{
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Log_DebugPrint("Emitting delay slot flush");
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EmitDelaySlotUpdate(true, false, false);
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m_load_delay_dirty = false;
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}
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}
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@ -528,9 +507,9 @@ bool CodeGenerator::Compile_Fallback(const CodeBlockInstruction& cbi)
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EmitFunctionCall(nullptr, &Thunks::InterpretInstruction, m_register_cache.GetCPUPtr());
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}
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m_current_instruction_in_branch_delay_slot_dirty = cbi.is_branch;
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m_branch_was_taken_dirty = cbi.is_branch;
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m_load_delay_dirty = true;
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m_current_instruction_in_branch_delay_slot_dirty = cbi.is_branch_instruction;
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m_branch_was_taken_dirty = cbi.is_branch_instruction;
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m_next_load_delay_dirty = cbi.has_load_delay;
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InstructionEpilogue(cbi);
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return true;
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}
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@ -147,6 +147,7 @@ private:
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void SyncCurrentInstructionPC();
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void SyncPC();
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void AddPendingCycles();
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void EmitDelaySlotUpdate(bool skip_check_for_delay, bool skip_check_old_value, bool move_next);
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//////////////////////////////////////////////////////////////////////////
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// Instruction Code Generators
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@ -172,14 +173,12 @@ private:
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std::array<Value, 3> m_operand_memory_addresses{};
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Xbyak::Label m_block_exit_label;
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// whether various flags need to be reset.
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bool m_current_instruction_in_branch_delay_slot_dirty = false;
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bool m_branch_was_taken_dirty = false;
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bool m_current_instruction_was_branch_taken_dirty = false;
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bool m_next_load_delay_dirty = false;
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bool m_load_delay_dirty = false;
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bool m_next_load_delay_dirty = false;
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};
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} // namespace CPU_X86::Recompiler
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@ -151,9 +151,8 @@ void CodeGenerator::EmitBeginBlock()
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|
||||
void CodeGenerator::EmitEndBlock()
|
||||
{
|
||||
m_emit.L(m_block_exit_label);
|
||||
m_register_cache.FreeHostReg(RCPUPTR);
|
||||
m_register_cache.PopCalleeSavedRegisters();
|
||||
m_register_cache.PopCalleeSavedRegisters(true);
|
||||
|
||||
m_emit.ret();
|
||||
}
|
||||
|
|
@ -166,9 +165,10 @@ void CodeGenerator::EmitBlockExitOnBool(const Value& value)
|
|||
m_emit.test(GetHostReg8(value), GetHostReg8(value));
|
||||
m_emit.jz(continue_label);
|
||||
|
||||
// flush current state
|
||||
// flush current state and return
|
||||
m_register_cache.FlushAllGuestRegisters(false, false);
|
||||
m_emit.jmp(m_block_exit_label, Xbyak::CodeGenerator::T_NEAR);
|
||||
m_register_cache.PopCalleeSavedRegisters(false);
|
||||
m_emit.ret();
|
||||
|
||||
m_emit.L(continue_label);
|
||||
}
|
||||
|
|
@ -1303,6 +1303,62 @@ void CodeGenerator::EmitAddCPUStructField(u32 offset, const Value& value)
|
|||
}
|
||||
}
|
||||
|
||||
void CodeGenerator::EmitDelaySlotUpdate(bool skip_check_for_delay, bool skip_check_old_value, bool move_next)
|
||||
{
|
||||
Value reg = m_register_cache.AllocateScratch(RegSize_8);
|
||||
Value value = m_register_cache.AllocateScratch(RegSize_32);
|
||||
|
||||
Xbyak::Label skip_flush;
|
||||
|
||||
auto load_delay_reg = m_emit.byte[GetCPUPtrReg() + offsetof(Core, m_load_delay_reg)];
|
||||
auto load_delay_old_value = m_emit.dword[GetCPUPtrReg() + offsetof(Core, m_load_delay_old_value)];
|
||||
auto load_delay_value = m_emit.dword[GetCPUPtrReg() + offsetof(Core, m_load_delay_value)];
|
||||
auto reg_ptr = m_emit.dword[GetCPUPtrReg() + offsetof(Core, m_regs.r[0]) + GetHostReg64(reg.host_reg) * 4];
|
||||
|
||||
// reg = load_delay_reg
|
||||
m_emit.movzx(GetHostReg32(reg.host_reg), load_delay_reg);
|
||||
if (!skip_check_old_value)
|
||||
m_emit.mov(GetHostReg32(value), load_delay_old_value);
|
||||
|
||||
if (!skip_check_for_delay)
|
||||
{
|
||||
// if load_delay_reg == Reg::count goto skip_flush
|
||||
m_emit.cmp(GetHostReg32(reg.host_reg), static_cast<u8>(Reg::count));
|
||||
m_emit.je(skip_flush);
|
||||
}
|
||||
|
||||
if (!skip_check_old_value)
|
||||
{
|
||||
// if r[reg] != load_delay_old_value goto skip_flush
|
||||
m_emit.cmp(GetHostReg32(value), reg_ptr);
|
||||
m_emit.jne(skip_flush);
|
||||
}
|
||||
|
||||
// r[reg] = load_delay_value
|
||||
m_emit.mov(GetHostReg32(value), load_delay_value);
|
||||
m_emit.mov(reg_ptr, GetHostReg32(value));
|
||||
|
||||
// if !move_next load_delay_reg = Reg::count
|
||||
if (!move_next)
|
||||
m_emit.mov(load_delay_reg, static_cast<u8>(Reg::count));
|
||||
|
||||
m_emit.L(skip_flush);
|
||||
|
||||
if (move_next)
|
||||
{
|
||||
auto next_load_delay_reg = m_emit.byte[GetCPUPtrReg() + offsetof(Core, m_next_load_delay_reg)];
|
||||
auto next_load_delay_old_value = m_emit.dword[GetCPUPtrReg() + offsetof(Core, m_next_load_delay_old_value)];
|
||||
auto next_load_delay_value = m_emit.dword[GetCPUPtrReg() + offsetof(Core, m_next_load_delay_value)];
|
||||
m_emit.mov(GetHostReg32(value), next_load_delay_value);
|
||||
m_emit.mov(GetHostReg8(reg), next_load_delay_reg);
|
||||
m_emit.mov(load_delay_value, GetHostReg32(value));
|
||||
m_emit.mov(GetHostReg32(value), next_load_delay_old_value);
|
||||
m_emit.mov(load_delay_reg, GetHostReg8(reg));
|
||||
m_emit.mov(load_delay_old_value, GetHostReg32(value));
|
||||
m_emit.mov(next_load_delay_reg, static_cast<u8>(Reg::count));
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
class ThunkGenerator
|
||||
{
|
||||
|
|
|
|||
|
|
@ -307,7 +307,7 @@ u32 RegisterCache::PopCallerSavedRegisters() const
|
|||
return count;
|
||||
}
|
||||
|
||||
u32 RegisterCache::PopCalleeSavedRegisters()
|
||||
u32 RegisterCache::PopCalleeSavedRegisters(bool commit)
|
||||
{
|
||||
if (m_host_register_callee_saved_order_count == 0)
|
||||
return 0;
|
||||
|
|
@ -321,7 +321,8 @@ u32 RegisterCache::PopCalleeSavedRegisters()
|
|||
(HostRegState::CalleeSaved | HostRegState::CalleeSavedAllocated));
|
||||
|
||||
m_code_generator.EmitPopHostReg(reg);
|
||||
m_host_register_state[reg] &= ~HostRegState::CalleeSavedAllocated;
|
||||
if (commit)
|
||||
m_host_register_state[reg] &= ~HostRegState::CalleeSavedAllocated;
|
||||
count++;
|
||||
i--;
|
||||
} while (i > 0);
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@ public:
|
|||
u32 PopCallerSavedRegisters() const;
|
||||
|
||||
/// Restore callee-saved registers. Call at the end of the function.
|
||||
u32 PopCalleeSavedRegisters();
|
||||
u32 PopCalleeSavedRegisters(bool commit);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
// Scratch Register Allocation
|
||||
|
|
|
|||
|
|
@ -40,4 +40,9 @@ bool Thunks::InterpretInstruction(Core* cpu)
|
|||
return cpu->m_exception_raised;
|
||||
}
|
||||
|
||||
void Thunks::UpdateLoadDelay(Core* cpu)
|
||||
{
|
||||
cpu->UpdateLoadDelay();
|
||||
}
|
||||
|
||||
} // namespace CPU::Recompiler
|
||||
|
|
@ -20,6 +20,7 @@ public:
|
|||
static bool WriteMemoryHalfWord(Core* cpu, u32 address, u16 value);
|
||||
static bool WriteMemoryWord(Core* cpu, u32 address, u32 value);
|
||||
static bool InterpretInstruction(Core* cpu);
|
||||
static void UpdateLoadDelay(Core* cpu);
|
||||
};
|
||||
|
||||
class ASMFunctions
|
||||
|
|
|
|||
|
|
@ -44,6 +44,76 @@ bool IsBranchInstruction(const Instruction& instruction)
|
|||
}
|
||||
}
|
||||
|
||||
bool IsMemoryLoadInstruction(const Instruction& instruction)
|
||||
{
|
||||
switch (instruction.op)
|
||||
{
|
||||
case InstructionOp::lb:
|
||||
case InstructionOp::lh:
|
||||
case InstructionOp::lw:
|
||||
case InstructionOp::lbu:
|
||||
case InstructionOp::lhu:
|
||||
case InstructionOp::lwl:
|
||||
case InstructionOp::lwr:
|
||||
return true;
|
||||
|
||||
case InstructionOp::lwc2:
|
||||
return true;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool IsMemoryStoreInstruction(const Instruction& instruction)
|
||||
{
|
||||
switch (instruction.op)
|
||||
{
|
||||
case InstructionOp::sb:
|
||||
case InstructionOp::sh:
|
||||
case InstructionOp::sw:
|
||||
case InstructionOp::swl:
|
||||
case InstructionOp::swr:
|
||||
return true;
|
||||
|
||||
case InstructionOp::swc2:
|
||||
return true;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool InstructionHasLoadDelay(const Instruction& instruction)
|
||||
{
|
||||
switch (instruction.op)
|
||||
{
|
||||
case InstructionOp::lb:
|
||||
case InstructionOp::lh:
|
||||
case InstructionOp::lw:
|
||||
case InstructionOp::lbu:
|
||||
case InstructionOp::lhu:
|
||||
case InstructionOp::lwl:
|
||||
case InstructionOp::lwr:
|
||||
return true;
|
||||
|
||||
case InstructionOp::cop0:
|
||||
case InstructionOp::cop2:
|
||||
{
|
||||
if (instruction.cop.IsCommonInstruction())
|
||||
{
|
||||
const CopCommonInstruction common_op = instruction.cop.CommonOp();
|
||||
return (common_op == CopCommonInstruction::cfcn || common_op == CopCommonInstruction::mfcn);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool IsExitBlockInstruction(const Instruction& instruction)
|
||||
{
|
||||
switch (instruction.op)
|
||||
|
|
@ -167,26 +237,6 @@ bool CanInstructionTrap(const Instruction& instruction, bool in_user_mode)
|
|||
}
|
||||
}
|
||||
|
||||
bool IsLoadDelayingInstruction(const Instruction& instruction)
|
||||
{
|
||||
switch (instruction.op)
|
||||
{
|
||||
case InstructionOp::lb:
|
||||
case InstructionOp::lh:
|
||||
case InstructionOp::lw:
|
||||
case InstructionOp::lbu:
|
||||
case InstructionOp::lhu:
|
||||
return true;
|
||||
|
||||
case InstructionOp::lwl:
|
||||
case InstructionOp::lwr:
|
||||
return false;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool IsInvalidInstruction(const Instruction& instruction)
|
||||
{
|
||||
// TODO
|
||||
|
|
|
|||
|
|
@ -208,9 +208,11 @@ union Instruction
|
|||
|
||||
// Instruction helpers.
|
||||
bool IsBranchInstruction(const Instruction& instruction);
|
||||
bool IsMemoryLoadInstruction(const Instruction& instruction);
|
||||
bool IsMemoryStoreInstruction(const Instruction& instruction);
|
||||
bool InstructionHasLoadDelay(const Instruction& instruction);
|
||||
bool IsExitBlockInstruction(const Instruction& instruction);
|
||||
bool CanInstructionTrap(const Instruction& instruction, bool in_user_mode);
|
||||
bool IsLoadDelayingInstruction(const Instruction& instruction);
|
||||
bool IsInvalidInstruction(const Instruction& instruction);
|
||||
|
||||
struct Registers
|
||||
|
|
@ -396,10 +398,13 @@ struct CodeBlockInstruction
|
|||
Instruction instruction;
|
||||
u32 pc;
|
||||
|
||||
bool is_branch : 1;
|
||||
bool is_branch_instruction : 1;
|
||||
bool is_branch_delay_slot : 1;
|
||||
bool is_load_instruction : 1;
|
||||
bool is_store_instruction : 1;
|
||||
bool is_load_delay_slot : 1;
|
||||
bool is_last_instruction : 1;
|
||||
bool has_load_delay : 1;
|
||||
bool can_trap : 1;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ bool System::Boot(const char* filename)
|
|||
void System::InitializeComponents()
|
||||
{
|
||||
m_cpu->Initialize(m_bus.get());
|
||||
m_cpu_code_cache->Initialize(m_cpu.get(), m_bus.get());
|
||||
m_cpu_code_cache->Initialize(this, m_cpu.get(), m_bus.get());
|
||||
m_bus->Initialize(m_cpu.get(), m_cpu_code_cache.get(), m_dma.get(), m_interrupt_controller.get(), m_gpu.get(),
|
||||
m_cdrom.get(), m_pad.get(), m_timers.get(), m_spu.get(), m_mdec.get());
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue