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GTE: Implement INTPL
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parent
1aa846e0f8
commit
55aefa2f27
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@ -274,6 +274,10 @@ void Core::ExecuteInstruction(Instruction inst)
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Execute_DPCS(inst);
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break;
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case 0x11:
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Execute_INTPL(inst);
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break;
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case 0x12:
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Execute_MVMVA(inst);
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break;
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@ -833,6 +837,38 @@ void Core::Execute_DPCL(Instruction inst)
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m_regs.FLAG.UpdateError();
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}
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void Core::Execute_INTPL(Instruction inst)
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{
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m_regs.FLAG.Clear();
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const u8 shift = inst.GetShift();
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const bool lm = inst.lm;
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// In: [IR1,IR2,IR3]=Vector, FC=Far Color, IR0=Interpolation value, CODE=MSB of RGBC
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// [MAC1,MAC2,MAC3] = [IR1,IR2,IR3] SHL 12 ;<--- for INTPL only
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// No need to assign these to MAC[1-3], as it'll never overflow.
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const s32 in_IR1 = s32(m_regs.IR1) << 12;
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const s32 in_IR2 = s32(m_regs.IR2) << 12;
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const s32 in_IR3 = s32(m_regs.IR3) << 12;
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// [MAC1,MAC2,MAC3] = MAC+(FC-MAC)*IR0
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// [IR1,IR2,IR3] = (([RFC,GFC,BFC] SHL 12) - [MAC1,MAC2,MAC3]) SAR (sf*12)
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TruncateAndSetMACAndIR<1>((s64(m_regs.FC[0]) << 12) - s64(in_IR1), shift, false);
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TruncateAndSetMACAndIR<2>((s64(m_regs.FC[1]) << 12) - s64(in_IR2), shift, false);
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TruncateAndSetMACAndIR<3>((s64(m_regs.FC[2]) << 12) - s64(in_IR3), shift, false);
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// [MAC1,MAC2,MAC3] = (([IR1,IR2,IR3] * IR0) + [MAC1,MAC2,MAC3])
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// [MAC1,MAC2,MAC3] = [MAC1,MAC2,MAC3] SAR (sf*12)
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TruncateAndSetMACAndIR<1>(s64(s32(m_regs.IR1) * s32(m_regs.IR0)) + s64(in_IR1), shift, lm);
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TruncateAndSetMACAndIR<2>(s64(s32(m_regs.IR2) * s32(m_regs.IR0)) + s64(in_IR2), shift, lm);
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TruncateAndSetMACAndIR<3>(s64(s32(m_regs.IR3) * s32(m_regs.IR0)) + s64(in_IR3), shift, lm);
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// Color FIFO = [MAC1/16,MAC2/16,MAC3/16,CODE], [IR1,IR2,IR3] = [MAC1,MAC2,MAC3]
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PushRGBFromMAC();
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m_regs.FLAG.UpdateError();
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}
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void Core::Execute_GPL(Instruction inst)
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{
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m_regs.FLAG.Clear();
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@ -86,6 +86,7 @@ private:
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void Execute_DPCS(Instruction inst);
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void Execute_DPCT(Instruction inst);
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void Execute_DPCL(Instruction inst);
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void Execute_INTPL(Instruction inst);
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void Execute_GPL(Instruction inst);
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void Execute_GPF(Instruction inst);
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