From 56dd9878e151dd5e604f581d6bd06fccbe93fa9a Mon Sep 17 00:00:00 2001
From: Stenzek <stenzek@gmail.com>
Date: Fri, 19 Jul 2024 22:23:13 +1000
Subject: [PATCH] Misc: RISC-V build fixes
---
src/common/gsvector_nosimd.h | 2 +-
src/core/spu.cpp | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/common/gsvector_nosimd.h b/src/common/gsvector_nosimd.h
index 3c6d73f81..7e0b8765a 100644
--- a/src/common/gsvector_nosimd.h
+++ b/src/common/gsvector_nosimd.h
@@ -115,7 +115,7 @@ public:
{
}
- ALWAYS_INLINE explicit GSVector2i(const GSVector2i& v) { std::memcpy(I32, v.I32, sizeof(I32)); }
+ ALWAYS_INLINE GSVector2i(const GSVector2i& v) { std::memcpy(I32, v.I32, sizeof(I32)); }
// MSVC has bad codegen for the constexpr version when applied to non-constexpr things (https://godbolt.org/z/h8qbn7),
// so leave the non-constexpr version default
diff --git a/src/core/spu.cpp b/src/core/spu.cpp
index f340e099d..d6b50483a 100644
--- a/src/core/spu.cpp
+++ b/src/core/spu.cpp
@@ -73,7 +73,7 @@ enum class RAMTransferMode : u8
DMARead = 3
};
-union SPUCNT
+union SPUCNTRegister
{
u16 bits;
@@ -91,7 +91,7 @@ union SPUCNT
BitField<u16, u8, 0, 6> mode;
};
-union SPUSTAT
+union SPUSTATRegister
{
u16 bits;
@@ -362,8 +362,8 @@ struct SPUState
TickCount cpu_ticks_per_spu_tick = 0;
TickCount cpu_tick_divider = 0;
- SPUCNT SPUCNT = {};
- SPUSTAT SPUSTAT = {};
+ SPUCNTRegister SPUCNT = {};
+ SPUSTATRegister SPUSTAT = {};
TransferControl transfer_control = {};
u16 transfer_address_reg = 0;
@@ -911,7 +911,7 @@ void SPU::WriteRegister(u32 offset, u16 value)
DEBUG_LOG("SPU control register <- 0x{:04X}", value);
GeneratePendingSamples();
- const SPUCNT new_value{value};
+ const SPUCNTRegister new_value{value};
if (new_value.ram_transfer_mode != s_state.SPUCNT.ram_transfer_mode &&
new_value.ram_transfer_mode == RAMTransferMode::Stopped)
{