mirror of
https://github.com/RetroDECK/Duckstation.git
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CPU: Use lookup tables for memory access
This commit is contained in:
Stenzek
parent
05fe925409
commit
56fc207af6
2429
src/core/bus.cpp
2429
src/core/bus.cpp
File diff suppressed because it is too large
Load diff
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@ -23,9 +23,12 @@ enum : u32
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RAM_8MB_SIZE = 0x800000,
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RAM_8MB_MASK = RAM_8MB_SIZE - 1,
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RAM_MIRROR_END = 0x800000,
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RAM_MIRROR_SIZE = 0x800000,
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EXP1_BASE = 0x1F000000,
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EXP1_SIZE = 0x800000,
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EXP1_MASK = EXP1_SIZE - 1,
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HW_BASE = 0x1F801000,
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HW_SIZE = 0x1000,
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MEMCTRL_BASE = 0x1F801000,
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MEMCTRL_SIZE = 0x40,
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MEMCTRL_MASK = MEMCTRL_SIZE - 1,
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@ -38,9 +41,9 @@ enum : u32
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MEMCTRL2_BASE = 0x1F801060,
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MEMCTRL2_SIZE = 0x10,
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MEMCTRL2_MASK = MEMCTRL2_SIZE - 1,
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INTERRUPT_CONTROLLER_BASE = 0x1F801070,
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INTERRUPT_CONTROLLER_SIZE = 0x10,
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INTERRUPT_CONTROLLER_MASK = INTERRUPT_CONTROLLER_SIZE - 1,
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INTC_BASE = 0x1F801070,
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INTC_SIZE = 0x10,
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INTERRUPT_CONTROLLER_MASK = INTC_SIZE - 1,
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DMA_BASE = 0x1F801080,
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DMA_SIZE = 0x80,
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DMA_MASK = DMA_SIZE - 1,
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@ -63,7 +66,7 @@ enum : u32
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EXP2_SIZE = 0x2000,
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EXP2_MASK = EXP2_SIZE - 1,
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EXP3_BASE = 0x1FA00000,
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EXP3_SIZE = 0x1,
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EXP3_SIZE = 0x200000,
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EXP3_MASK = EXP3_SIZE - 1,
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BIOS_BASE = 0x1FC00000,
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BIOS_SIZE = 0x80000,
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@ -85,6 +88,11 @@ enum : u32
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RAM_2MB_CODE_PAGE_COUNT = (RAM_2MB_SIZE + (HOST_PAGE_SIZE + 1)) / HOST_PAGE_SIZE,
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RAM_8MB_CODE_PAGE_COUNT = (RAM_8MB_SIZE + (HOST_PAGE_SIZE + 1)) / HOST_PAGE_SIZE,
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MEMORY_LUT_PAGE_SIZE = 4096,
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MEMORY_LUT_PAGE_SHIFT = 12,
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MEMORY_LUT_SIZE = 0x100000, // 0x100000000 >> 12
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MEMORY_LUT_SLOTS = MEMORY_LUT_SIZE * 3 * 2, // [size][read_write]
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FASTMEM_LUT_PAGE_SIZE = 4096,
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FASTMEM_LUT_PAGE_MASK = FASTMEM_LUT_PAGE_SIZE - 1,
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FASTMEM_LUT_PAGE_SHIFT = 12,
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@ -105,18 +113,35 @@ void Shutdown();
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void Reset();
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bool DoState(StateWrapper& sw);
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using MemoryReadHandler = u32 (*)(VirtualMemoryAddress address);
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using MemoryWriteHandler = void (*)(VirtualMemoryAddress, u32);
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void** GetMemoryHandlers(bool isolate_cache, bool swap_caches);
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template<typename FP>
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ALWAYS_INLINE_RELEASE static FP* OffsetHandlerArray(void** handlers, MemoryAccessSize size, MemoryAccessType type)
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{
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return reinterpret_cast<FP*>(handlers +
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(((static_cast<size_t>(size) * 2) + static_cast<size_t>(type)) * MEMORY_LUT_SIZE));
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}
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CPUFastmemMode GetFastmemMode();
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u8* GetFastmemBase();
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void* GetFastmemBase();
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void UpdateFastmemViews(CPUFastmemMode mode);
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bool CanUseFastmemForAddress(VirtualMemoryAddress address);
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void SetExpansionROM(std::vector<u8> data);
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extern std::bitset<RAM_8MB_CODE_PAGE_COUNT> g_ram_code_bits;
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extern u8* g_ram; // 2MB-8MB RAM
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extern u32 g_ram_size; // Active size of RAM.
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extern u32 g_ram_mask; // Active address bits for RAM.
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extern u8 g_bios[BIOS_SIZE]; // 512K BIOS ROM
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extern u8* g_ram; // 2MB-8MB RAM
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extern u32 g_ram_size; // Active size of RAM.
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extern u32 g_ram_mask; // Active address bits for RAM.
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extern u8* g_bios; // 512K BIOS ROM
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extern std::array<TickCount, 3> g_exp1_access_time;
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extern std::array<TickCount, 3> g_exp2_access_time;
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extern std::array<TickCount, 3> g_bios_access_time;
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extern std::array<TickCount, 3> g_cdrom_access_time;
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extern std::array<TickCount, 3> g_spu_access_time;
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/// Returns true if the address specified is writable (RAM).
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ALWAYS_INLINE static bool IsRAMAddress(PhysicalMemoryAddress address)
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@ -263,8 +263,7 @@ void Initialize()
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}
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#endif
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AllocateFastMap();
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AllocateFastMap();
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#ifdef ENABLE_RECOMPILER
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if (g_settings.IsUsingRecompiler())
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@ -531,7 +530,9 @@ void Flush()
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}
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#ifndef _MSC_VER
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void __debugbreak() {}
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void __debugbreak()
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{
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}
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#endif
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void LogCurrentState()
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@ -1127,7 +1128,7 @@ bool InitializeFastmem()
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}
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Bus::UpdateFastmemViews(mode);
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CPU::UpdateFastmemBase();
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CPU::UpdateMemoryPointers();
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return true;
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}
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@ -1135,21 +1136,22 @@ void ShutdownFastmem()
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{
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Common::PageFaultHandler::RemoveHandler(&s_host_code_map);
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Bus::UpdateFastmemViews(CPUFastmemMode::Disabled);
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CPU::UpdateFastmemBase();
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CPU::UpdateMemoryPointers();
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}
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#ifdef ENABLE_MMAP_FASTMEM
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Common::PageFaultHandler::HandlerResult MMapPageFaultHandler(void* exception_pc, void* fault_address, bool is_write)
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{
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if (static_cast<u8*>(fault_address) < g_state.fastmem_base ||
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(static_cast<u8*>(fault_address) - g_state.fastmem_base) >= static_cast<ptrdiff_t>(Bus::FASTMEM_ARENA_SIZE))
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if (static_cast<u8*>(fault_address) < static_cast<u8*>(g_state.fastmem_base) ||
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(static_cast<u8*>(fault_address) - static_cast<u8*>(g_state.fastmem_base)) >=
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static_cast<ptrdiff_t>(Bus::FASTMEM_ARENA_SIZE))
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{
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return Common::PageFaultHandler::HandlerResult::ExecuteNextHandler;
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}
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const PhysicalMemoryAddress fastmem_address =
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static_cast<PhysicalMemoryAddress>(static_cast<ptrdiff_t>(static_cast<u8*>(fault_address) - g_state.fastmem_base));
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const PhysicalMemoryAddress fastmem_address = static_cast<PhysicalMemoryAddress>(
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static_cast<ptrdiff_t>(static_cast<u8*>(fault_address) - static_cast<u8*>(g_state.fastmem_base)));
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Log_DevPrintf("Page fault handler invoked at PC=%p Address=%p %s, fastmem offset 0x%08X", exception_pc, fault_address,
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is_write ? "(write)" : "(read)", fastmem_address);
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@ -63,6 +63,21 @@ static void ExecuteInstruction();
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template<PGXPMode pgxp_mode, bool debug>
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[[noreturn]] static void ExecuteImpl();
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static bool FetchInstruction();
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static bool FetchInstructionForInterpreterFallback();
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template<bool add_ticks, bool icache_read = false, u32 word_count = 1, bool raise_exceptions>
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static bool DoInstructionRead(PhysicalMemoryAddress address, void* data);
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template<MemoryAccessType type, MemoryAccessSize size>
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static bool DoSafeMemoryAccess(VirtualMemoryAddress address, u32& value);
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template<MemoryAccessType type, MemoryAccessSize size>
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static bool DoAlignmentCheck(VirtualMemoryAddress address);
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static bool ReadMemoryByte(VirtualMemoryAddress addr, u8* value);
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static bool ReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value);
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static bool ReadMemoryWord(VirtualMemoryAddress addr, u32* value);
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static bool WriteMemoryByte(VirtualMemoryAddress addr, u32 value);
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static bool WriteMemoryHalfWord(VirtualMemoryAddress addr, u32 value);
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static bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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State g_state;
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bool TRACE_EXECUTION = false;
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@ -139,7 +154,7 @@ void CPU::Initialize()
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s_last_breakpoint_check_pc = INVALID_BREAKPOINT_PC;
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s_single_step = false;
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UpdateFastmemBase();
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UpdateMemoryPointers();
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GTE::Initialize();
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}
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@ -154,6 +169,8 @@ void CPU::Reset()
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{
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g_state.pending_ticks = 0;
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g_state.downcount = 0;
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g_state.exception_raised = false;
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g_state.bus_error = false;
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g_state.regs = {};
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@ -168,7 +185,7 @@ void CPU::Reset()
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g_state.cop0_regs.cause.bits = 0;
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ClearICache();
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UpdateFastmemBase();
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UpdateMemoryPointers();
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GTE::Reset();
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@ -202,6 +219,7 @@ bool CPU::DoState(StateWrapper& sw)
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sw.Do(&g_state.next_instruction_is_branch_delay_slot);
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sw.Do(&g_state.branch_was_taken);
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sw.Do(&g_state.exception_raised);
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sw.DoEx(&g_state.bus_error, 61, false);
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if (sw.GetVersion() < 59)
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{
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bool interrupt_delay;
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@ -240,21 +258,13 @@ bool CPU::DoState(StateWrapper& sw)
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if (sw.IsReading())
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{
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UpdateFastmemBase();
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UpdateMemoryPointers();
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g_state.gte_completion_tick = 0;
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}
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return !sw.HasError();
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}
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void CPU::UpdateFastmemBase()
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{
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if (g_state.cop0_regs.sr.Isc)
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g_state.fastmem_base = nullptr;
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else
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g_state.fastmem_base = Bus::GetFastmemBase();
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}
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ALWAYS_INLINE_RELEASE void CPU::SetPC(u32 new_pc)
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{
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DebugAssert(Common::IsAlignedPow2(new_pc, 4));
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@ -527,6 +537,7 @@ ALWAYS_INLINE_RELEASE void CPU::WriteCop0Reg(Cop0Reg reg, u32 value)
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g_state.cop0_regs.sr.bits =
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(g_state.cop0_regs.sr.bits & ~Cop0Registers::SR::WRITE_MASK) | (value & Cop0Registers::SR::WRITE_MASK);
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Log_DebugPrintf("COP0 SR <- %08X (now %08X)", value, g_state.cop0_regs.sr.bits);
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UpdateMemoryPointers();
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CheckForPendingInterrupt();
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}
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break;
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@ -2357,3 +2368,904 @@ bool CPU::Recompiler::Thunks::InterpretInstructionPGXP()
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ExecuteInstruction<PGXPMode::Memory, false>();
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return g_state.exception_raised;
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}
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ALWAYS_INLINE_RELEASE Bus::MemoryReadHandler CPU::GetMemoryReadHandler(VirtualMemoryAddress address,
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MemoryAccessSize size)
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{
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Bus::MemoryReadHandler* base =
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Bus::OffsetHandlerArray<Bus::MemoryReadHandler>(g_state.memory_handlers, size, MemoryAccessType::Read);
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return base[address >> Bus::MEMORY_LUT_PAGE_SHIFT];
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}
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ALWAYS_INLINE_RELEASE Bus::MemoryWriteHandler CPU::GetMemoryWriteHandler(VirtualMemoryAddress address,
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MemoryAccessSize size)
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{
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Bus::MemoryWriteHandler* base =
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Bus::OffsetHandlerArray<Bus::MemoryWriteHandler>(g_state.memory_handlers, size, MemoryAccessType::Write);
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return base[address >> Bus::MEMORY_LUT_PAGE_SHIFT];
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}
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void CPU::UpdateMemoryPointers()
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{
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g_state.memory_handlers = Bus::GetMemoryHandlers(g_state.cop0_regs.sr.Isc, g_state.cop0_regs.sr.Swc);
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g_state.fastmem_base = g_state.cop0_regs.sr.Isc ? nullptr : Bus::GetFastmemBase();
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}
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void CPU::ExecutionModeChanged()
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{
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g_state.bus_error = false;
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}
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template<bool add_ticks, bool icache_read, u32 word_count, bool raise_exceptions>
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ALWAYS_INLINE_RELEASE bool CPU::DoInstructionRead(PhysicalMemoryAddress address, void* data)
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{
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using namespace Bus;
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address &= PHYSICAL_MEMORY_ADDRESS_MASK;
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if (address < RAM_MIRROR_END)
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{
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std::memcpy(data, &g_ram[address & g_ram_mask], sizeof(u32) * word_count);
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if constexpr (add_ticks)
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g_state.pending_ticks += (icache_read ? 1 : RAM_READ_TICKS) * word_count;
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return true;
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}
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else if (address >= BIOS_BASE && address < (BIOS_BASE + BIOS_SIZE))
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{
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std::memcpy(data, &g_bios[(address - BIOS_BASE) & BIOS_MASK], sizeof(u32) * word_count);
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if constexpr (add_ticks)
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g_state.pending_ticks += g_bios_access_time[static_cast<u32>(MemoryAccessSize::Word)] * word_count;
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return true;
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}
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else
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{
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if (raise_exceptions)
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CPU::RaiseException(address, Cop0Registers::CAUSE::MakeValueForException(Exception::IBE, false, false, 0));
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std::memset(data, 0, sizeof(u32) * word_count);
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return false;
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}
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}
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TickCount CPU::GetInstructionReadTicks(VirtualMemoryAddress address)
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{
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using namespace Bus;
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address &= PHYSICAL_MEMORY_ADDRESS_MASK;
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if (address < RAM_MIRROR_END)
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{
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return RAM_READ_TICKS;
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}
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else if (address >= BIOS_BASE && address < (BIOS_BASE + BIOS_SIZE))
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{
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return g_bios_access_time[static_cast<u32>(MemoryAccessSize::Word)];
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}
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else
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{
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return 0;
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}
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}
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TickCount CPU::GetICacheFillTicks(VirtualMemoryAddress address)
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{
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using namespace Bus;
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address &= PHYSICAL_MEMORY_ADDRESS_MASK;
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if (address < RAM_MIRROR_END)
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{
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return 1 * ((ICACHE_LINE_SIZE - (address & (ICACHE_LINE_SIZE - 1))) / sizeof(u32));
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}
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else if (address >= BIOS_BASE && address < (BIOS_BASE + BIOS_SIZE))
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{
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return g_bios_access_time[static_cast<u32>(MemoryAccessSize::Word)] *
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((ICACHE_LINE_SIZE - (address & (ICACHE_LINE_SIZE - 1))) / sizeof(u32));
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}
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else
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{
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return 0;
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}
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}
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void CPU::CheckAndUpdateICacheTags(u32 line_count, TickCount uncached_ticks)
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{
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VirtualMemoryAddress current_pc = g_state.pc & ICACHE_TAG_ADDRESS_MASK;
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if (IsCachedAddress(current_pc))
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{
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TickCount ticks = 0;
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TickCount cached_ticks_per_line = GetICacheFillTicks(current_pc);
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for (u32 i = 0; i < line_count; i++, current_pc += ICACHE_LINE_SIZE)
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{
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const u32 line = GetICacheLine(current_pc);
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if (g_state.icache_tags[line] != current_pc)
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{
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g_state.icache_tags[line] = current_pc;
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ticks += cached_ticks_per_line;
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}
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}
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g_state.pending_ticks += ticks;
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}
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else
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{
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g_state.pending_ticks += uncached_ticks;
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}
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}
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u32 CPU::FillICache(VirtualMemoryAddress address)
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{
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const u32 line = GetICacheLine(address);
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u8* line_data = &g_state.icache_data[line * ICACHE_LINE_SIZE];
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u32 line_tag;
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switch ((address >> 2) & 0x03u)
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{
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case 0:
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DoInstructionRead<true, true, 4, false>(address & ~(ICACHE_LINE_SIZE - 1u), line_data);
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line_tag = GetICacheTagForAddress(address);
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break;
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case 1:
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DoInstructionRead<true, true, 3, false>(address & (~(ICACHE_LINE_SIZE - 1u) | 0x4), line_data + 0x4);
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line_tag = GetICacheTagForAddress(address) | 0x1;
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break;
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case 2:
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DoInstructionRead<true, true, 2, false>(address & (~(ICACHE_LINE_SIZE - 1u) | 0x8), line_data + 0x8);
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line_tag = GetICacheTagForAddress(address) | 0x3;
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break;
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case 3:
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default:
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DoInstructionRead<true, true, 1, false>(address & (~(ICACHE_LINE_SIZE - 1u) | 0xC), line_data + 0xC);
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line_tag = GetICacheTagForAddress(address) | 0x7;
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break;
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}
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g_state.icache_tags[line] = line_tag;
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const u32 offset = GetICacheLineOffset(address);
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u32 result;
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std::memcpy(&result, &line_data[offset], sizeof(result));
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return result;
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}
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void CPU::ClearICache()
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{
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std::memset(g_state.icache_data.data(), 0, ICACHE_SIZE);
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g_state.icache_tags.fill(ICACHE_INVALID_BITS);
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}
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namespace CPU {
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ALWAYS_INLINE_RELEASE static u32 ReadICache(VirtualMemoryAddress address)
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{
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const u32 line = GetICacheLine(address);
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const u8* line_data = &g_state.icache_data[line * ICACHE_LINE_SIZE];
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const u32 offset = GetICacheLineOffset(address);
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u32 result;
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std::memcpy(&result, &line_data[offset], sizeof(result));
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return result;
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}
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} // namespace CPU
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ALWAYS_INLINE_RELEASE bool CPU::FetchInstruction()
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{
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DebugAssert(Common::IsAlignedPow2(g_state.npc, 4));
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const PhysicalMemoryAddress address = g_state.npc;
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switch (address >> 29)
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{
|
||||
case 0x00: // KUSEG 0M-512M
|
||||
case 0x04: // KSEG0 - physical memory cached
|
||||
{
|
||||
#if 0
|
||||
DoInstructionRead<true, false, 1, false>(address, &g_state.next_instruction.bits);
|
||||
#else
|
||||
if (CompareICacheTag(address))
|
||||
g_state.next_instruction.bits = ReadICache(address);
|
||||
else
|
||||
g_state.next_instruction.bits = FillICache(address);
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x05: // KSEG1 - physical memory uncached
|
||||
{
|
||||
if (!DoInstructionRead<true, false, 1, true>(address, &g_state.next_instruction.bits))
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x01: // KUSEG 512M-1024M
|
||||
case 0x02: // KUSEG 1024M-1536M
|
||||
case 0x03: // KUSEG 1536M-2048M
|
||||
case 0x06: // KSEG2
|
||||
case 0x07: // KSEG2
|
||||
default:
|
||||
{
|
||||
CPU::RaiseException(Cop0Registers::CAUSE::MakeValueForException(Exception::IBE,
|
||||
g_state.current_instruction_in_branch_delay_slot,
|
||||
g_state.current_instruction_was_branch_taken, 0),
|
||||
address);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
g_state.pc = g_state.npc;
|
||||
g_state.npc += sizeof(g_state.next_instruction.bits);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::FetchInstructionForInterpreterFallback()
|
||||
{
|
||||
DebugAssert(Common::IsAlignedPow2(g_state.npc, 4));
|
||||
|
||||
const PhysicalMemoryAddress address = g_state.npc;
|
||||
switch (address >> 29)
|
||||
{
|
||||
case 0x00: // KUSEG 0M-512M
|
||||
case 0x04: // KSEG0 - physical memory cached
|
||||
case 0x05: // KSEG1 - physical memory uncached
|
||||
{
|
||||
// We don't use the icache when doing interpreter fallbacks, because it's probably stale.
|
||||
if (!DoInstructionRead<false, false, 1, true>(address, &g_state.next_instruction.bits))
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x01: // KUSEG 512M-1024M
|
||||
case 0x02: // KUSEG 1024M-1536M
|
||||
case 0x03: // KUSEG 1536M-2048M
|
||||
case 0x06: // KSEG2
|
||||
case 0x07: // KSEG2
|
||||
default:
|
||||
{
|
||||
CPU::RaiseException(Cop0Registers::CAUSE::MakeValueForException(Exception::IBE,
|
||||
g_state.current_instruction_in_branch_delay_slot,
|
||||
g_state.current_instruction_was_branch_taken, 0),
|
||||
address);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
g_state.pc = g_state.npc;
|
||||
g_state.npc += sizeof(g_state.next_instruction.bits);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::SafeReadInstruction(VirtualMemoryAddress addr, u32* value)
|
||||
{
|
||||
switch (addr >> 29)
|
||||
{
|
||||
case 0x00: // KUSEG 0M-512M
|
||||
case 0x04: // KSEG0 - physical memory cached
|
||||
case 0x05: // KSEG1 - physical memory uncached
|
||||
{
|
||||
// TODO: Check icache.
|
||||
return DoInstructionRead<false, false, 1, false>(addr, value);
|
||||
}
|
||||
|
||||
case 0x01: // KUSEG 512M-1024M
|
||||
case 0x02: // KUSEG 1024M-1536M
|
||||
case 0x03: // KUSEG 1536M-2048M
|
||||
case 0x06: // KSEG2
|
||||
case 0x07: // KSEG2
|
||||
default:
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
template<MemoryAccessType type, MemoryAccessSize size>
|
||||
ALWAYS_INLINE bool CPU::DoSafeMemoryAccess(VirtualMemoryAddress address, u32& value)
|
||||
{
|
||||
using namespace Bus;
|
||||
|
||||
switch (address >> 29)
|
||||
{
|
||||
case 0x00: // KUSEG 0M-512M
|
||||
case 0x04: // KSEG0 - physical memory cached
|
||||
{
|
||||
address &= PHYSICAL_MEMORY_ADDRESS_MASK;
|
||||
if ((address & DCACHE_LOCATION_MASK) == DCACHE_LOCATION)
|
||||
{
|
||||
const u32 offset = address & DCACHE_OFFSET_MASK;
|
||||
|
||||
if constexpr (type == MemoryAccessType::Read)
|
||||
{
|
||||
if constexpr (size == MemoryAccessSize::Byte)
|
||||
{
|
||||
value = CPU::g_state.dcache[offset];
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::HalfWord)
|
||||
{
|
||||
u16 temp;
|
||||
std::memcpy(&temp, &CPU::g_state.dcache[offset], sizeof(u16));
|
||||
value = ZeroExtend32(temp);
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::Word)
|
||||
{
|
||||
std::memcpy(&value, &CPU::g_state.dcache[offset], sizeof(u32));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if constexpr (size == MemoryAccessSize::Byte)
|
||||
{
|
||||
CPU::g_state.dcache[offset] = Truncate8(value);
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::HalfWord)
|
||||
{
|
||||
std::memcpy(&CPU::g_state.dcache[offset], &value, sizeof(u16));
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::Word)
|
||||
{
|
||||
std::memcpy(&CPU::g_state.dcache[offset], &value, sizeof(u32));
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x01: // KUSEG 512M-1024M
|
||||
case 0x02: // KUSEG 1024M-1536M
|
||||
case 0x03: // KUSEG 1536M-2048M
|
||||
case 0x06: // KSEG2
|
||||
case 0x07: // KSEG2
|
||||
{
|
||||
// Above 512mb raises an exception.
|
||||
return false;
|
||||
}
|
||||
|
||||
case 0x05: // KSEG1 - physical memory uncached
|
||||
{
|
||||
address &= PHYSICAL_MEMORY_ADDRESS_MASK;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (address < RAM_MIRROR_END)
|
||||
{
|
||||
const u32 offset = address & g_ram_mask;
|
||||
if constexpr (type == MemoryAccessType::Read)
|
||||
{
|
||||
if constexpr (size == MemoryAccessSize::Byte)
|
||||
{
|
||||
value = g_ram[offset];
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::HalfWord)
|
||||
{
|
||||
u16 temp;
|
||||
std::memcpy(&temp, &g_ram[offset], sizeof(temp));
|
||||
value = ZeroExtend32(temp);
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::Word)
|
||||
{
|
||||
std::memcpy(&value, &g_ram[offset], sizeof(u32));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
const u32 page_index = offset / HOST_PAGE_SIZE;
|
||||
|
||||
if constexpr (size == MemoryAccessSize::Byte)
|
||||
{
|
||||
if (g_ram[offset] != Truncate8(value))
|
||||
{
|
||||
g_ram[offset] = Truncate8(value);
|
||||
if (g_ram_code_bits[page_index])
|
||||
CPU::CodeCache::InvalidateBlocksWithPageIndex(page_index);
|
||||
}
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::HalfWord)
|
||||
{
|
||||
const u16 new_value = Truncate16(value);
|
||||
u16 old_value;
|
||||
std::memcpy(&old_value, &g_ram[offset], sizeof(old_value));
|
||||
if (old_value != new_value)
|
||||
{
|
||||
std::memcpy(&g_ram[offset], &new_value, sizeof(u16));
|
||||
if (g_ram_code_bits[page_index])
|
||||
CPU::CodeCache::InvalidateBlocksWithPageIndex(page_index);
|
||||
}
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::Word)
|
||||
{
|
||||
u32 old_value;
|
||||
std::memcpy(&old_value, &g_ram[offset], sizeof(u32));
|
||||
if (old_value != value)
|
||||
{
|
||||
std::memcpy(&g_ram[offset], &value, sizeof(u32));
|
||||
if (g_ram_code_bits[page_index])
|
||||
CPU::CodeCache::InvalidateBlocksWithPageIndex(page_index);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
if constexpr (type == MemoryAccessType::Read)
|
||||
{
|
||||
if (address >= BIOS_BASE && address < (BIOS_BASE + BIOS_SIZE))
|
||||
{
|
||||
const u32 offset = (address & BIOS_MASK);
|
||||
if constexpr (size == MemoryAccessSize::Byte)
|
||||
{
|
||||
value = ZeroExtend32(g_bios[offset]);
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::HalfWord)
|
||||
{
|
||||
u16 halfword;
|
||||
std::memcpy(&halfword, &g_bios[offset], sizeof(u16));
|
||||
value = ZeroExtend32(halfword);
|
||||
}
|
||||
else
|
||||
{
|
||||
std::memcpy(&value, &g_bios[offset], sizeof(u32));
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool CPU::SafeReadMemoryByte(VirtualMemoryAddress addr, u8* value)
|
||||
{
|
||||
u32 temp = 0;
|
||||
if (!DoSafeMemoryAccess<MemoryAccessType::Read, MemoryAccessSize::Byte>(addr, temp))
|
||||
return false;
|
||||
|
||||
*value = Truncate8(temp);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::SafeReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value)
|
||||
{
|
||||
if ((addr & 1) == 0)
|
||||
{
|
||||
u32 temp = 0;
|
||||
if (!DoSafeMemoryAccess<MemoryAccessType::Read, MemoryAccessSize::HalfWord>(addr, temp))
|
||||
return false;
|
||||
|
||||
*value = Truncate16(temp);
|
||||
return true;
|
||||
}
|
||||
|
||||
u8 low, high;
|
||||
if (!SafeReadMemoryByte(addr, &low) || !SafeReadMemoryByte(addr + 1, &high))
|
||||
return false;
|
||||
|
||||
*value = (ZeroExtend16(high) << 8) | ZeroExtend16(low);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::SafeReadMemoryWord(VirtualMemoryAddress addr, u32* value)
|
||||
{
|
||||
if ((addr & 3) == 0)
|
||||
return DoSafeMemoryAccess<MemoryAccessType::Read, MemoryAccessSize::Word>(addr, *value);
|
||||
|
||||
u16 low, high;
|
||||
if (!SafeReadMemoryHalfWord(addr, &low) || !SafeReadMemoryHalfWord(addr + 2, &high))
|
||||
return false;
|
||||
|
||||
*value = (ZeroExtend32(high) << 16) | ZeroExtend32(low);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::SafeReadMemoryCString(VirtualMemoryAddress addr, std::string* value, u32 max_length /*= 1024*/)
|
||||
{
|
||||
value->clear();
|
||||
|
||||
u8 ch;
|
||||
while (SafeReadMemoryByte(addr, &ch))
|
||||
{
|
||||
if (ch == 0)
|
||||
return true;
|
||||
|
||||
value->push_back(ch);
|
||||
if (value->size() >= max_length)
|
||||
return true;
|
||||
|
||||
addr++;
|
||||
}
|
||||
|
||||
value->clear();
|
||||
return false;
|
||||
}
|
||||
|
||||
bool CPU::SafeWriteMemoryByte(VirtualMemoryAddress addr, u8 value)
|
||||
{
|
||||
u32 temp = ZeroExtend32(value);
|
||||
return DoSafeMemoryAccess<MemoryAccessType::Write, MemoryAccessSize::Byte>(addr, temp);
|
||||
}
|
||||
|
||||
bool CPU::SafeWriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value)
|
||||
{
|
||||
if ((addr & 1) == 0)
|
||||
{
|
||||
u32 temp = ZeroExtend32(value);
|
||||
return DoSafeMemoryAccess<MemoryAccessType::Write, MemoryAccessSize::HalfWord>(addr, temp);
|
||||
}
|
||||
|
||||
return SafeWriteMemoryByte(addr, Truncate8(value)) && SafeWriteMemoryByte(addr + 1, Truncate8(value >> 8));
|
||||
}
|
||||
|
||||
bool CPU::SafeWriteMemoryWord(VirtualMemoryAddress addr, u32 value)
|
||||
{
|
||||
if ((addr & 3) == 0)
|
||||
return DoSafeMemoryAccess<MemoryAccessType::Write, MemoryAccessSize::Word>(addr, value);
|
||||
|
||||
return SafeWriteMemoryHalfWord(addr, Truncate16(value >> 16)) &&
|
||||
SafeWriteMemoryHalfWord(addr + 2, Truncate16(value >> 16));
|
||||
}
|
||||
|
||||
void* CPU::GetDirectReadMemoryPointer(VirtualMemoryAddress address, MemoryAccessSize size, TickCount* read_ticks)
|
||||
{
|
||||
using namespace Bus;
|
||||
|
||||
const u32 seg = (address >> 29);
|
||||
if (seg != 0 && seg != 4 && seg != 5)
|
||||
return nullptr;
|
||||
|
||||
const PhysicalMemoryAddress paddr = address & PHYSICAL_MEMORY_ADDRESS_MASK;
|
||||
if (paddr < RAM_MIRROR_END)
|
||||
{
|
||||
if (read_ticks)
|
||||
*read_ticks = RAM_READ_TICKS;
|
||||
|
||||
return &g_ram[paddr & g_ram_mask];
|
||||
}
|
||||
|
||||
if ((paddr & DCACHE_LOCATION_MASK) == DCACHE_LOCATION)
|
||||
{
|
||||
if (read_ticks)
|
||||
*read_ticks = 0;
|
||||
|
||||
return &g_state.dcache[paddr & DCACHE_OFFSET_MASK];
|
||||
}
|
||||
|
||||
if (paddr >= BIOS_BASE && paddr < (BIOS_BASE + BIOS_SIZE))
|
||||
{
|
||||
if (read_ticks)
|
||||
*read_ticks = g_bios_access_time[static_cast<u32>(size)];
|
||||
|
||||
return &g_bios[paddr & BIOS_MASK];
|
||||
}
|
||||
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
void* CPU::GetDirectWriteMemoryPointer(VirtualMemoryAddress address, MemoryAccessSize size)
|
||||
{
|
||||
using namespace Bus;
|
||||
|
||||
const u32 seg = (address >> 29);
|
||||
if (seg != 0 && seg != 4 && seg != 5)
|
||||
return nullptr;
|
||||
|
||||
const PhysicalMemoryAddress paddr = address & PHYSICAL_MEMORY_ADDRESS_MASK;
|
||||
|
||||
#if 0
|
||||
// Not enabled until we can protect code regions.
|
||||
if (paddr < RAM_MIRROR_END)
|
||||
return &g_ram[paddr & RAM_MASK];
|
||||
#endif
|
||||
|
||||
if ((paddr & DCACHE_LOCATION_MASK) == DCACHE_LOCATION)
|
||||
return &g_state.dcache[paddr & DCACHE_OFFSET_MASK];
|
||||
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
template<MemoryAccessType type, MemoryAccessSize size>
|
||||
ALWAYS_INLINE_RELEASE bool CPU::DoAlignmentCheck(VirtualMemoryAddress address)
|
||||
{
|
||||
if constexpr (size == MemoryAccessSize::HalfWord)
|
||||
{
|
||||
if (Common::IsAlignedPow2(address, 2))
|
||||
return true;
|
||||
}
|
||||
else if constexpr (size == MemoryAccessSize::Word)
|
||||
{
|
||||
if (Common::IsAlignedPow2(address, 4))
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
g_state.cop0_regs.BadVaddr = address;
|
||||
RaiseException(type == MemoryAccessType::Read ? Exception::AdEL : Exception::AdES);
|
||||
return false;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void MemoryBreakpoint(MemoryAccessType type, MemoryAccessSize size, VirtualMemoryAddress addr, u32 value)
|
||||
{
|
||||
static constexpr const char* sizes[3] = { "byte", "halfword", "word" };
|
||||
static constexpr const char* types[2] = { "read", "write" };
|
||||
|
||||
const u32 cycle = TimingEvents::GetGlobalTickCounter() + CPU::g_state.pending_ticks;
|
||||
|
||||
#if 0
|
||||
static std::FILE* fp = nullptr;
|
||||
if (!fp)
|
||||
fp = std::fopen("D:\\memory.txt", "wb");
|
||||
if (fp)
|
||||
{
|
||||
std::fprintf(fp, "%u %s %s %08X %08X\n", cycle, types[static_cast<u32>(type)], sizes[static_cast<u32>(size)], addr, value);
|
||||
std::fflush(fp);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
if (type == MemoryAccessType::Read && addr == 0x1F000084)
|
||||
__debugbreak();
|
||||
#endif
|
||||
#if 0
|
||||
if (type == MemoryAccessType::Write && addr == 0x000000B0 /*&& value == 0x3C080000*/)
|
||||
__debugbreak();
|
||||
#endif
|
||||
|
||||
#if 0 // TODO: MEMBP
|
||||
if (type == MemoryAccessType::Write && address == 0x80113028)
|
||||
{
|
||||
if ((TimingEvents::GetGlobalTickCounter() + CPU::g_state.pending_ticks) == 5051485)
|
||||
__debugbreak();
|
||||
|
||||
Log_WarningPrintf("VAL %08X @ %u", value, (TimingEvents::GetGlobalTickCounter() + CPU::g_state.pending_ticks));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#define MEMORY_BREAKPOINT(type, size, addr, value) MemoryBreakpoint((type), (size), (addr), (value))
|
||||
#else
|
||||
#define MEMORY_BREAKPOINT(type, size, addr, value)
|
||||
#endif
|
||||
|
||||
bool CPU::ReadMemoryByte(VirtualMemoryAddress addr, u8* value)
|
||||
{
|
||||
*value = Truncate8(GetMemoryReadHandler(addr, MemoryAccessSize::Byte)(addr));
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
RaiseException(Exception::DBE);
|
||||
return false;
|
||||
}
|
||||
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Read, MemoryAccessSize::Byte, addr, *value);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::ReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value)
|
||||
{
|
||||
if (!DoAlignmentCheck<MemoryAccessType::Read, MemoryAccessSize::HalfWord>(addr))
|
||||
return false;
|
||||
|
||||
*value = Truncate16(GetMemoryReadHandler(addr, MemoryAccessSize::HalfWord)(addr));
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
RaiseException(Exception::DBE);
|
||||
return false;
|
||||
}
|
||||
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Read, MemoryAccessSize::HalfWord, addr, *value);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::ReadMemoryWord(VirtualMemoryAddress addr, u32* value)
|
||||
{
|
||||
if (!DoAlignmentCheck<MemoryAccessType::Read, MemoryAccessSize::Word>(addr))
|
||||
return false;
|
||||
|
||||
*value = GetMemoryReadHandler(addr, MemoryAccessSize::Word)(addr);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
RaiseException(Exception::DBE);
|
||||
return false;
|
||||
}
|
||||
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Read, MemoryAccessSize::Word, addr, *value);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::WriteMemoryByte(VirtualMemoryAddress addr, u32 value)
|
||||
{
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Write, MemoryAccessSize::Byte, addr, value);
|
||||
|
||||
GetMemoryWriteHandler(addr, MemoryAccessSize::Byte)(addr, value);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
RaiseException(Exception::DBE);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::WriteMemoryHalfWord(VirtualMemoryAddress addr, u32 value)
|
||||
{
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Write, MemoryAccessSize::HalfWord, addr, value);
|
||||
|
||||
if (!DoAlignmentCheck<MemoryAccessType::Write, MemoryAccessSize::HalfWord>(addr))
|
||||
return false;
|
||||
|
||||
GetMemoryWriteHandler(addr, MemoryAccessSize::HalfWord)(addr, value);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
RaiseException(Exception::DBE);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool CPU::WriteMemoryWord(VirtualMemoryAddress addr, u32 value)
|
||||
{
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Write, MemoryAccessSize::Word, addr, value);
|
||||
|
||||
if (!DoAlignmentCheck<MemoryAccessType::Write, MemoryAccessSize::Word>(addr))
|
||||
return false;
|
||||
|
||||
GetMemoryWriteHandler(addr, MemoryAccessSize::Word)(addr, value);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
RaiseException(Exception::DBE);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
u64 CPU::Recompiler::Thunks::ReadMemoryByte(u32 address)
|
||||
{
|
||||
const u32 value = GetMemoryReadHandler(address, MemoryAccessSize::Byte)(address);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
return static_cast<u64>(-static_cast<s64>(Exception::DBE));
|
||||
}
|
||||
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Read, MemoryAccessSize::Byte, address, value);
|
||||
return ZeroExtend64(value);
|
||||
}
|
||||
|
||||
u64 CPU::Recompiler::Thunks::ReadMemoryHalfWord(u32 address)
|
||||
{
|
||||
if (!Common::IsAlignedPow2(address, 2)) [[unlikely]]
|
||||
{
|
||||
g_state.cop0_regs.BadVaddr = address;
|
||||
return static_cast<u64>(-static_cast<s64>(Exception::AdEL));
|
||||
}
|
||||
|
||||
const u32 value = GetMemoryReadHandler(address, MemoryAccessSize::HalfWord)(address);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
return static_cast<u64>(-static_cast<s64>(Exception::DBE));
|
||||
}
|
||||
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Read, MemoryAccessSize::HalfWord, address, value);
|
||||
return ZeroExtend64(value);
|
||||
}
|
||||
|
||||
u64 CPU::Recompiler::Thunks::ReadMemoryWord(u32 address)
|
||||
{
|
||||
if (!Common::IsAlignedPow2(address, 4)) [[unlikely]]
|
||||
{
|
||||
g_state.cop0_regs.BadVaddr = address;
|
||||
return static_cast<u64>(-static_cast<s64>(Exception::AdEL));
|
||||
}
|
||||
|
||||
const u32 value = GetMemoryReadHandler(address, MemoryAccessSize::Word)(address);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
return static_cast<u64>(-static_cast<s64>(Exception::DBE));
|
||||
}
|
||||
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Read, MemoryAccessSize::Word, address, value);
|
||||
return ZeroExtend64(value);
|
||||
}
|
||||
|
||||
u32 CPU::Recompiler::Thunks::WriteMemoryByte(u32 address, u32 value)
|
||||
{
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Write, MemoryAccessSize::Byte, address, value);
|
||||
|
||||
GetMemoryWriteHandler(address, MemoryAccessSize::Byte)(address, value);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
return static_cast<u32>(Exception::DBE);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 CPU::Recompiler::Thunks::WriteMemoryHalfWord(u32 address, u32 value)
|
||||
{
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Write, MemoryAccessSize::HalfWord, address, value);
|
||||
|
||||
if (!Common::IsAlignedPow2(address, 2)) [[unlikely]]
|
||||
{
|
||||
g_state.cop0_regs.BadVaddr = address;
|
||||
return static_cast<u32>(Exception::AdES);
|
||||
}
|
||||
|
||||
GetMemoryWriteHandler(address, MemoryAccessSize::HalfWord)(address, value);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
return static_cast<u32>(Exception::DBE);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 CPU::Recompiler::Thunks::WriteMemoryWord(u32 address, u32 value)
|
||||
{
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Write, MemoryAccessSize::Word, address, value);
|
||||
|
||||
if (!Common::IsAlignedPow2(address, 4)) [[unlikely]]
|
||||
{
|
||||
g_state.cop0_regs.BadVaddr = address;
|
||||
return static_cast<u32>(Exception::AdES);
|
||||
}
|
||||
|
||||
GetMemoryWriteHandler(address, MemoryAccessSize::Word)(address, value);
|
||||
if (g_state.bus_error) [[unlikely]]
|
||||
{
|
||||
g_state.bus_error = false;
|
||||
return static_cast<u32>(Exception::DBE);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 CPU::Recompiler::Thunks::UncheckedReadMemoryByte(u32 address)
|
||||
{
|
||||
const u32 value = GetMemoryReadHandler(address, MemoryAccessSize::Byte)(address);
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Read, MemoryAccessSize::Byte, address, value);
|
||||
return value;
|
||||
}
|
||||
|
||||
u32 CPU::Recompiler::Thunks::UncheckedReadMemoryHalfWord(u32 address)
|
||||
{
|
||||
const u32 value = GetMemoryReadHandler(address, MemoryAccessSize::HalfWord)(address);
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Read, MemoryAccessSize::HalfWord, address, value);
|
||||
return value;
|
||||
}
|
||||
|
||||
u32 CPU::Recompiler::Thunks::UncheckedReadMemoryWord(u32 address)
|
||||
{
|
||||
const u32 value = GetMemoryReadHandler(address, MemoryAccessSize::Word)(address);
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Read, MemoryAccessSize::Word, address, value);
|
||||
return value;
|
||||
}
|
||||
|
||||
void CPU::Recompiler::Thunks::UncheckedWriteMemoryByte(u32 address, u32 value)
|
||||
{
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Write, MemoryAccessSize::Byte, address, value);
|
||||
GetMemoryWriteHandler(address, MemoryAccessSize::Byte)(address, value);
|
||||
}
|
||||
|
||||
void CPU::Recompiler::Thunks::UncheckedWriteMemoryHalfWord(u32 address, u32 value)
|
||||
{
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Write, MemoryAccessSize::HalfWord, address, value);
|
||||
GetMemoryWriteHandler(address, MemoryAccessSize::HalfWord)(address, value);
|
||||
}
|
||||
|
||||
void CPU::Recompiler::Thunks::UncheckedWriteMemoryWord(u32 address, u32 value)
|
||||
{
|
||||
MEMORY_BREAKPOINT(MemoryAccessType::Write, MemoryAccessSize::Word, address, value);
|
||||
GetMemoryWriteHandler(address, MemoryAccessSize::Word)(address, value);
|
||||
}
|
||||
|
||||
#undef MEMORY_BREAKPOINT
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ struct State
|
|||
bool next_instruction_is_branch_delay_slot = false;
|
||||
bool branch_was_taken = false;
|
||||
bool exception_raised = false;
|
||||
bool bus_error = false;
|
||||
|
||||
// load delays
|
||||
Reg load_delay_reg = Reg::count;
|
||||
|
|
@ -84,7 +85,8 @@ struct State
|
|||
// 4 bytes of padding here on x64
|
||||
bool use_debug_dispatcher = false;
|
||||
|
||||
u8* fastmem_base = nullptr;
|
||||
void* fastmem_base = nullptr;
|
||||
void** memory_handlers = nullptr;
|
||||
|
||||
// data cache (used as scratchpad)
|
||||
std::array<u8, DCACHE_SIZE> dcache = {};
|
||||
|
|
@ -102,7 +104,8 @@ void Shutdown();
|
|||
void Reset();
|
||||
bool DoState(StateWrapper& sw);
|
||||
void ClearICache();
|
||||
void UpdateFastmemBase();
|
||||
void UpdateMemoryPointers();
|
||||
void ExecutionModeChanged();
|
||||
|
||||
/// Executes interpreter loop.
|
||||
void Execute();
|
||||
|
|
|
|||
|
|
@ -102,16 +102,11 @@ ALWAYS_INLINE static VirtualMemoryAddress PhysicalAddressToVirtual(PhysicalMemor
|
|||
return bases[static_cast<u32>(segment)] | address;
|
||||
}
|
||||
|
||||
// defined in bus.cpp - memory access functions which return false if an exception was thrown.
|
||||
bool FetchInstruction();
|
||||
bool FetchInstructionForInterpreterFallback();
|
||||
Bus::MemoryReadHandler GetMemoryReadHandler(VirtualMemoryAddress address, MemoryAccessSize size);
|
||||
Bus::MemoryWriteHandler GetMemoryWriteHandler(VirtualMemoryAddress address, MemoryAccessSize size);
|
||||
|
||||
// memory access functions which return false if an exception was thrown.
|
||||
bool SafeReadInstruction(VirtualMemoryAddress addr, u32* value);
|
||||
bool ReadMemoryByte(VirtualMemoryAddress addr, u8* value);
|
||||
bool ReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value);
|
||||
bool ReadMemoryWord(VirtualMemoryAddress addr, u32* value);
|
||||
bool WriteMemoryByte(VirtualMemoryAddress addr, u32 value);
|
||||
bool WriteMemoryHalfWord(VirtualMemoryAddress addr, u32 value);
|
||||
bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
|
||||
void* GetDirectReadMemoryPointer(VirtualMemoryAddress address, MemoryAccessSize size, TickCount* read_ticks);
|
||||
void* GetDirectWriteMemoryPointer(VirtualMemoryAddress address, MemoryAccessSize size);
|
||||
|
||||
|
|
|
|||
|
|
@ -2687,18 +2687,18 @@ bool CodeGenerator::Compile_cop0(const CodeBlockInstruction& cbi)
|
|||
m_speculative_constants.cop0_sr = SpeculativeReadReg(cbi.instruction.r.rt);
|
||||
|
||||
// changing SR[Isc] needs to update fastmem views
|
||||
if (reg == Cop0Reg::SR && g_settings.IsUsingFastmem())
|
||||
if (reg == Cop0Reg::SR)
|
||||
{
|
||||
LabelType skip_fastmem_update;
|
||||
LabelType skip_mem_update;
|
||||
Value old_value = m_register_cache.AllocateScratch(RegSize_32);
|
||||
EmitLoadCPUStructField(old_value.host_reg, RegSize_32, offset);
|
||||
EmitStoreCPUStructField(offset, value);
|
||||
EmitXor(old_value.host_reg, old_value.host_reg, value);
|
||||
EmitBranchIfBitClear(old_value.host_reg, RegSize_32, 16, &skip_fastmem_update);
|
||||
EmitBranchIfBitClear(old_value.host_reg, RegSize_32, 16, &skip_mem_update);
|
||||
m_register_cache.InhibitAllocation();
|
||||
EmitFunctionCall(nullptr, &UpdateFastmemBase, m_register_cache.GetCPUPtr());
|
||||
EmitFunctionCall(nullptr, &UpdateMemoryPointers, m_register_cache.GetCPUPtr());
|
||||
EmitUpdateFastmemBase();
|
||||
EmitBindLabel(&skip_fastmem_update);
|
||||
EmitBindLabel(&skip_mem_update);
|
||||
m_register_cache.UninhibitAllocation();
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
#include "types.h"
|
||||
|
||||
static constexpr u32 SAVE_STATE_MAGIC = 0x43435544;
|
||||
static constexpr u32 SAVE_STATE_VERSION = 60;
|
||||
static constexpr u32 SAVE_STATE_VERSION = 61;
|
||||
static constexpr u32 SAVE_STATE_MINIMUM_VERSION = 42;
|
||||
|
||||
static_assert(SAVE_STATE_VERSION >= SAVE_STATE_MINIMUM_VERSION);
|
||||
|
|
|
|||
|
|
@ -3510,6 +3510,7 @@ void System::CheckForSettingsChanges(const Settings& old_settings)
|
|||
TRANSLATE_SV("CPUExecutionMode", Settings::GetCPUExecutionModeDisplayName(
|
||||
g_settings.cpu_execution_mode))),
|
||||
5.0f);
|
||||
CPU::ExecutionModeChanged();
|
||||
CPU::CodeCache::Reinitialize();
|
||||
CPU::ClearICache();
|
||||
}
|
||||
|
|
@ -3521,6 +3522,7 @@ void System::CheckForSettingsChanges(const Settings& old_settings)
|
|||
g_settings.bios_tty_logging != old_settings.bios_tty_logging))
|
||||
{
|
||||
Host::AddOSDMessage(TRANSLATE_STR("OSDMessage", "Recompiler options changed, flushing all blocks."), 5.0f);
|
||||
CPU::ExecutionModeChanged();
|
||||
|
||||
// changing memory exceptions can re-enable fastmem
|
||||
if (g_settings.cpu_recompiler_memory_exceptions != old_settings.cpu_recompiler_memory_exceptions)
|
||||
|
|
|
|||
Loading…
Reference in a new issue