From 75f206262c3e476ed6aa72a2e0ccf7f7bb1d3f13 Mon Sep 17 00:00:00 2001 From: Connor McLaughlin Date: Fri, 18 Oct 2019 23:10:41 +1000 Subject: [PATCH] Pad: Store JOY_BAUD --- src/core/bus.cpp | 19 +++++++++---------- src/core/pad.cpp | 7 ++++++- src/core/pad.h | 1 + 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/core/bus.cpp b/src/core/bus.cpp index 56e9d5f6f..9d9da929c 100644 --- a/src/core/bus.cpp +++ b/src/core/bus.cpp @@ -137,7 +137,6 @@ TickCount Bus::ReadWords(PhysicalMemoryAddress address, u32* words, u32 word_cou return total_ticks; } - // DMA is using DRAM Hyper Page mode, allowing it to access DRAM rows at 1 clock cycle per word (effectively around 17 // clks per 16 words, due to required row address loading, probably plus some further minimal overload due to refresh // cycles). This is making DMA much faster than CPU memory accesses (CPU DRAM access takes 1 opcode cycle plus 6 @@ -272,15 +271,15 @@ void Bus::RecalculateMemoryTimings() std::tie(m_spu_access_time[0], m_spu_access_time[1], m_spu_access_time[2]) = CalculateMemoryTiming(m_MEMCTRL.spu_delay_size, m_MEMCTRL.common_delay); - Log_DevPrintf("BIOS Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d", - m_MEMCTRL.bios_delay_size.data_bus_16bit ? 16 : 8, m_bios_access_time[0], m_bios_access_time[1], - m_bios_access_time[2]); - Log_DevPrintf("CDROM Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d", - m_MEMCTRL.cdrom_delay_size.data_bus_16bit ? 16 : 8, m_cdrom_access_time[0], m_cdrom_access_time[1], - m_cdrom_access_time[2]); - Log_DevPrintf("SPU Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d", - m_MEMCTRL.spu_delay_size.data_bus_16bit ? 16 : 8, m_spu_access_time[0], m_spu_access_time[1], - m_spu_access_time[2]); + Log_TracePrintf("BIOS Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d", + m_MEMCTRL.bios_delay_size.data_bus_16bit ? 16 : 8, m_bios_access_time[0], m_bios_access_time[1], + m_bios_access_time[2]); + Log_TracePrintf("CDROM Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d", + m_MEMCTRL.cdrom_delay_size.data_bus_16bit ? 16 : 8, m_cdrom_access_time[0], m_cdrom_access_time[1], + m_cdrom_access_time[2]); + Log_TracePrintf("SPU Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d", + m_MEMCTRL.spu_delay_size.data_bus_16bit ? 16 : 8, m_spu_access_time[0], m_spu_access_time[1], + m_spu_access_time[2]); } TickCount Bus::DoInvalidAccess(MemoryAccessType type, MemoryAccessSize size, PhysicalMemoryAddress address, u32& value) diff --git a/src/core/pad.cpp b/src/core/pad.cpp index 638e77152..5d60fed2c 100644 --- a/src/core/pad.cpp +++ b/src/core/pad.cpp @@ -63,6 +63,7 @@ bool Pad::DoState(StateWrapper& sw) sw.Do(&m_JOY_CTRL.bits); sw.Do(&m_JOY_STAT.bits); sw.Do(&m_JOY_MODE.bits); + sw.Do(&m_JOY_BAUD); sw.Do(&m_RX_FIFO); sw.Do(&m_TX_FIFO); return !sw.HasError(); @@ -99,6 +100,9 @@ u32 Pad::ReadRegister(u32 offset) case 0x0A: // JOY_CTRL return ZeroExtend32(m_JOY_CTRL.bits); + case 0x0E: // JOY_BAUD + return ZeroExtend32(m_JOY_BAUD); + default: Log_ErrorPrintf("Unknown register read: 0x%X", offset); return UINT32_C(0xFFFFFFFF); @@ -167,7 +171,8 @@ void Pad::WriteRegister(u32 offset, u32 value) case 0x0E: { - Log_WarningPrintf("JOY_BAUD <- 0x%08X", value); + Log_DebugPrintf("JOY_BAUD <- 0x%08X", value); + m_JOY_BAUD = value; return; } diff --git a/src/core/pad.h b/src/core/pad.h index 6ca20bde7..8fc03e371 100644 --- a/src/core/pad.h +++ b/src/core/pad.h @@ -110,6 +110,7 @@ private: JOY_CTRL m_JOY_CTRL = {}; JOY_STAT m_JOY_STAT = {}; JOY_MODE m_JOY_MODE = {}; + u16 m_JOY_BAUD = 0; ActiveDevice m_active_device = ActiveDevice::None; InlineFIFOQueue m_RX_FIFO;