mirror of
https://github.com/RetroDECK/Duckstation.git
synced 2025-03-04 06:20:54 +00:00
CPU: Fix GTE control register disassembly
This commit is contained in:
parent
0065800f05
commit
884c851079
src
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@ -51,9 +51,9 @@ static bool BreakpointCheck();
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static void TracePrintInstruction();
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static void TracePrintInstruction();
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#endif
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#endif
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static void DisassembleAndPrint(u32 addr, const char* prefix);
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static void DisassembleAndPrint(u32 addr, bool regs, const char* prefix);
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static void PrintInstruction(u32 bits, u32 pc, Registers* regs, const char* prefix);
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static void PrintInstruction(u32 bits, u32 pc, bool regs, const char* prefix);
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static void LogInstruction(u32 bits, u32 pc, Registers* regs);
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static void LogInstruction(u32 bits, u32 pc, bool regs);
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static void HandleWriteSyscall();
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static void HandleWriteSyscall();
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static void HandlePutcSyscall();
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static void HandlePutcSyscall();
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@ -314,7 +314,7 @@ ALWAYS_INLINE_RELEASE void CPU::RaiseException(u32 CAUSE_bits, u32 EPC, u32 vect
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static_cast<u8>(g_state.cop0_regs.cause.Excode.GetValue()), g_state.current_instruction_pc,
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static_cast<u8>(g_state.cop0_regs.cause.Excode.GetValue()), g_state.current_instruction_pc,
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g_state.cop0_regs.EPC, g_state.cop0_regs.cause.BD ? "true" : "false",
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g_state.cop0_regs.EPC, g_state.cop0_regs.cause.BD ? "true" : "false",
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g_state.cop0_regs.cause.CE.GetValue());
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g_state.cop0_regs.cause.CE.GetValue());
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DisassembleAndPrint(g_state.current_instruction_pc, 4, 0);
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DisassembleAndPrint(g_state.current_instruction_pc, 4u, 0u);
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if (s_trace_to_log)
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if (s_trace_to_log)
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{
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{
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CPU::WriteToExecutionLog("Exception %u at 0x%08X (epc=0x%08X, BD=%s, CE=%u)\n",
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CPU::WriteToExecutionLog("Exception %u at 0x%08X (epc=0x%08X, BD=%s, CE=%u)\n",
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@ -669,7 +669,7 @@ void CPU::TracePrintInstruction()
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TinyString instr;
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TinyString instr;
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TinyString comment;
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TinyString comment;
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DisassembleInstruction(&instr, pc, bits);
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DisassembleInstruction(&instr, pc, bits);
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DisassembleInstructionComment(&comment, pc, bits, &g_state.regs);
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DisassembleInstructionComment(&comment, pc, bits);
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if (!comment.empty())
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if (!comment.empty())
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{
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{
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for (u32 i = instr.length(); i < 30; i++)
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for (u32 i = instr.length(); i < 30; i++)
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@ -683,35 +683,41 @@ void CPU::TracePrintInstruction()
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#endif
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#endif
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void CPU::PrintInstruction(u32 bits, u32 pc, Registers* regs, const char* prefix)
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void CPU::PrintInstruction(u32 bits, u32 pc, bool regs, const char* prefix)
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{
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{
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TinyString instr;
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TinyString instr;
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TinyString comment;
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DisassembleInstruction(&instr, pc, bits);
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DisassembleInstruction(&instr, pc, bits);
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DisassembleInstructionComment(&comment, pc, bits, regs);
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if (regs)
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if (!comment.empty())
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{
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{
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for (u32 i = instr.length(); i < 30; i++)
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TinyString comment;
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instr.append(' ');
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DisassembleInstructionComment(&comment, pc, bits);
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instr.append("; ");
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if (!comment.empty())
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instr.append(comment);
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{
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for (u32 i = instr.length(); i < 30; i++)
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instr.append(' ');
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instr.append("; ");
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instr.append(comment);
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}
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}
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}
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Log_DevPrintf("%s%08x: %08x %s", prefix, pc, bits, instr.c_str());
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Log_DevPrintf("%s%08x: %08x %s", prefix, pc, bits, instr.c_str());
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}
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}
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void CPU::LogInstruction(u32 bits, u32 pc, Registers* regs)
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void CPU::LogInstruction(u32 bits, u32 pc, bool regs)
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{
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{
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TinyString instr;
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TinyString instr;
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TinyString comment;
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DisassembleInstruction(&instr, pc, bits);
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DisassembleInstruction(&instr, pc, bits);
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DisassembleInstructionComment(&comment, pc, bits, regs);
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if (regs)
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if (!comment.empty())
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{
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{
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for (u32 i = instr.length(); i < 30; i++)
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TinyString comment;
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instr.append(' ');
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DisassembleInstructionComment(&comment, pc, bits);
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instr.append("; ");
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if (!comment.empty())
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instr.append(comment);
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{
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for (u32 i = instr.length(); i < 30; i++)
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instr.append(' ');
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instr.append("; ");
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instr.append(comment);
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}
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}
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}
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WriteToExecutionLog("%08x: %08x %s\n", pc, bits, instr.c_str());
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WriteToExecutionLog("%08x: %08x %s\n", pc, bits, instr.c_str());
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@ -899,11 +905,11 @@ ALWAYS_INLINE static constexpr bool SubOverflow(u32 old_value, u32 sub_value, u3
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return (((new_value ^ old_value) & (old_value ^ sub_value)) & UINT32_C(0x80000000)) != 0;
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return (((new_value ^ old_value) & (old_value ^ sub_value)) & UINT32_C(0x80000000)) != 0;
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}
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}
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void CPU::DisassembleAndPrint(u32 addr, const char* prefix)
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void CPU::DisassembleAndPrint(u32 addr, bool regs, const char* prefix)
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{
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{
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u32 bits = 0;
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u32 bits = 0;
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SafeReadMemoryWord(addr, &bits);
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SafeReadMemoryWord(addr, &bits);
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PrintInstruction(bits, addr, &g_state.regs, prefix);
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PrintInstruction(bits, addr, regs, prefix);
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}
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}
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void CPU::DisassembleAndPrint(u32 addr, u32 instructions_before /* = 0 */, u32 instructions_after /* = 0 */)
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void CPU::DisassembleAndPrint(u32 addr, u32 instructions_before /* = 0 */, u32 instructions_after /* = 0 */)
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@ -911,14 +917,14 @@ void CPU::DisassembleAndPrint(u32 addr, u32 instructions_before /* = 0 */, u32 i
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u32 disasm_addr = addr - (instructions_before * sizeof(u32));
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u32 disasm_addr = addr - (instructions_before * sizeof(u32));
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for (u32 i = 0; i < instructions_before; i++)
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for (u32 i = 0; i < instructions_before; i++)
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{
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{
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DisassembleAndPrint(disasm_addr, "");
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DisassembleAndPrint(disasm_addr, false, "");
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disasm_addr += sizeof(u32);
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disasm_addr += sizeof(u32);
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}
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}
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// <= to include the instruction itself
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// <= to include the instruction itself
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for (u32 i = 0; i <= instructions_after; i++)
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for (u32 i = 0; i <= instructions_after; i++)
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{
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{
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DisassembleAndPrint(disasm_addr, (i == 0) ? "---->" : "");
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DisassembleAndPrint(disasm_addr, (i == 0), (i == 0) ? "---->" : "");
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disasm_addr += sizeof(u32);
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disasm_addr += sizeof(u32);
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}
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}
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}
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}
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@ -2227,7 +2233,7 @@ template<PGXPMode pgxp_mode, bool debug>
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if constexpr (debug)
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if constexpr (debug)
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{
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{
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if (s_trace_to_log)
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if (s_trace_to_log)
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LogInstruction(g_state.current_instruction.bits, g_state.current_instruction_pc, &g_state.regs);
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LogInstruction(g_state.current_instruction.bits, g_state.current_instruction_pc, true);
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if (g_state.current_instruction_pc == 0xA0) [[unlikely]]
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if (g_state.current_instruction_pc == 0xA0) [[unlikely]]
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HandleA0Syscall();
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HandleA0Syscall();
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@ -42,14 +42,14 @@ struct GTEInstructionTable
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} // namespace
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} // namespace
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static void FormatInstruction(SmallStringBase* dest, const Instruction inst, u32 pc, const char* format);
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static void FormatInstruction(SmallStringBase* dest, const Instruction inst, u32 pc, const char* format);
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static void FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, Registers* regs, const char* format);
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static void FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, const char* format);
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template<typename T>
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template<typename T>
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static void FormatCopInstruction(SmallStringBase* dest, u32 pc, const Instruction inst,
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static void FormatCopInstruction(SmallStringBase* dest, u32 pc, const Instruction inst,
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const std::pair<T, const char*>* table, size_t table_size, T table_key);
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const std::pair<T, const char*>* table, size_t table_size, T table_key);
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template<typename T>
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template<typename T>
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static void FormatCopComment(SmallStringBase* dest, u32 pc, Registers* regs, const Instruction inst,
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static void FormatCopComment(SmallStringBase* dest, u32 pc, const Instruction inst,
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const std::pair<T, const char*>* table, size_t table_size, T table_key);
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const std::pair<T, const char*>* table, size_t table_size, T table_key);
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static void FormatGTEInstruction(SmallStringBase* dest, u32 pc, const Instruction inst);
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static void FormatGTEInstruction(SmallStringBase* dest, u32 pc, const Instruction inst);
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@ -189,10 +189,10 @@ static const std::array<const char*, 64> s_special_table = {{
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}};
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}};
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static const std::array<std::pair<CopCommonInstruction, const char*>, 4> s_cop_common_table = {
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static const std::array<std::pair<CopCommonInstruction, const char*>, 4> s_cop_common_table = {
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{{CopCommonInstruction::mfcn, "mfc$cop $rt, $coprd"},
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{{CopCommonInstruction::mfcn, "mfc$cop $rt_, $coprd"},
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{CopCommonInstruction::cfcn, "cfc$cop $rt, $coprd"},
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{CopCommonInstruction::cfcn, "cfc$cop $rt_, $coprdc"},
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{CopCommonInstruction::mtcn, "mtc$cop $rt, $coprd"},
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{CopCommonInstruction::mtcn, "mtc$cop $rt, $coprd"},
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{CopCommonInstruction::ctcn, "ctc$cop $rt, $coprd"}}};
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{CopCommonInstruction::ctcn, "ctc$cop $rt, $coprdc"}}};
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static const std::array<std::pair<Cop0Instruction, const char*>, 1> s_cop0_table = {{{Cop0Instruction::rfe, "rfe"}}};
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static const std::array<std::pair<Cop0Instruction, const char*>, 1> s_cop0_table = {{{Cop0Instruction::rfe, "rfe"}}};
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@ -291,6 +291,11 @@ void CPU::FormatInstruction(SmallStringBase* dest, const Instruction inst, u32 p
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dest->append(GetRegName(inst.r.rs));
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dest->append(GetRegName(inst.r.rs));
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str += 2;
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str += 2;
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}
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}
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else if (std::strncmp(str, "rt_", 3) == 0)
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{
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dest->append(GetRegName(inst.r.rt));
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str += 3;
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}
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else if (std::strncmp(str, "rt", 2) == 0)
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else if (std::strncmp(str, "rt", 2) == 0)
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{
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{
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dest->append(GetRegName(inst.r.rt));
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dest->append(GetRegName(inst.r.rt));
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@ -340,6 +345,14 @@ void CPU::FormatInstruction(SmallStringBase* dest, const Instruction inst, u32 p
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dest->append(((inst.bits & (UINT32_C(1) << 24)) != 0) ? 't' : 'f');
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dest->append(((inst.bits & (UINT32_C(1) << 24)) != 0) ? 't' : 'f');
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str += 5;
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str += 5;
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}
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}
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else if (std::strncmp(str, "coprdc", 6) == 0)
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{
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if (inst.IsCop2Instruction())
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dest->append(GetGTERegisterName(static_cast<u8>(inst.r.rd.GetValue()) + 32));
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else
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dest->append_format("{}", ZeroExtend32(static_cast<u8>(inst.r.rd.GetValue())));
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str += 6;
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}
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else if (std::strncmp(str, "coprd", 5) == 0)
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else if (std::strncmp(str, "coprd", 5) == 0)
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{
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{
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if (inst.IsCop2Instruction())
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if (inst.IsCop2Instruction())
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@ -368,8 +381,10 @@ void CPU::FormatInstruction(SmallStringBase* dest, const Instruction inst, u32 p
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}
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}
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}
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}
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void CPU::FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, Registers* regs, const char* format)
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void CPU::FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, const char* format)
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{
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{
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const CPU::Registers* regs = &CPU::g_state.regs;
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const char* str = format;
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const char* str = format;
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while (*str != '\0')
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while (*str != '\0')
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{
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{
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@ -384,6 +399,10 @@ void CPU::FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, R
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str += 2;
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str += 2;
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}
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}
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else if (std::strncmp(str, "rt_", 3) == 0)
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{
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str += 3;
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}
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else if (std::strncmp(str, "rt", 2) == 0)
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else if (std::strncmp(str, "rt", 2) == 0)
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{
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{
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dest->append_format("{}{}=0x{:08X}", dest->empty() ? "" : ", ", GetRegName(inst.r.rt),
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dest->append_format("{}{}=0x{:08X}", dest->empty() ? "" : ", ", GetRegName(inst.r.rt),
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@ -427,12 +446,36 @@ void CPU::FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, R
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{
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{
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str += 5;
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str += 5;
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}
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}
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else if (std::strncmp(str, "coprdc", 6) == 0)
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{
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if (inst.IsCop2Instruction())
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{
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dest->append_format("{}{}=0x{:08X}", dest->empty() ? "" : ", ",
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GetGTERegisterName(static_cast<u8>(inst.r.rd.GetValue()) + 32),
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g_state.gte_regs.cr32[static_cast<u8>(inst.r.rd.GetValue())]);
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}
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str += 6;
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}
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else if (std::strncmp(str, "coprd", 5) == 0)
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else if (std::strncmp(str, "coprd", 5) == 0)
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{
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{
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if (inst.IsCop2Instruction())
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{
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dest->append_format("{}{}=0x{:08X}", dest->empty() ? "" : ", ",
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GetGTERegisterName(static_cast<u8>(inst.r.rd.GetValue())),
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g_state.gte_regs.dr32[static_cast<u8>(inst.r.rd.GetValue())]);
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}
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str += 5;
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str += 5;
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}
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}
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else if (std::strncmp(str, "coprt", 5) == 0)
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else if (std::strncmp(str, "coprt", 5) == 0)
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{
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{
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if (inst.IsCop2Instruction())
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{
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dest->append_format("{}{}=0x{:08X}", dest->empty() ? "" : ", ",
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GetGTERegisterName(static_cast<u8>(inst.r.rt.GetValue())),
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g_state.gte_regs.dr32[static_cast<u8>(inst.r.rt.GetValue())]);
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}
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str += 5;
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str += 5;
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}
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}
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else if (std::strncmp(str, "cop", 3) == 0)
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else if (std::strncmp(str, "cop", 3) == 0)
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@ -463,14 +506,14 @@ void CPU::FormatCopInstruction(SmallStringBase* dest, u32 pc, const Instruction
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}
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}
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template<typename T>
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template<typename T>
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void CPU::FormatCopComment(SmallStringBase* dest, u32 pc, Registers* regs, const Instruction inst,
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void CPU::FormatCopComment(SmallStringBase* dest, u32 pc, const Instruction inst,
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const std::pair<T, const char*>* table, size_t table_size, T table_key)
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const std::pair<T, const char*>* table, size_t table_size, T table_key)
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{
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{
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for (size_t i = 0; i < table_size; i++)
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for (size_t i = 0; i < table_size; i++)
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{
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{
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if (table[i].first == table_key)
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if (table[i].first == table_key)
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{
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{
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FormatComment(dest, inst, pc, regs, table[i].second);
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FormatComment(dest, inst, pc, table[i].second);
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return;
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return;
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}
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}
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}
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}
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@ -560,13 +603,13 @@ void CPU::DisassembleInstruction(SmallStringBase* dest, u32 pc, u32 bits)
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}
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}
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}
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}
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void CPU::DisassembleInstructionComment(SmallStringBase* dest, u32 pc, u32 bits, Registers* regs)
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void CPU::DisassembleInstructionComment(SmallStringBase* dest, u32 pc, u32 bits)
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{
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{
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const Instruction inst{bits};
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const Instruction inst{bits};
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switch (inst.op)
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switch (inst.op)
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{
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{
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case InstructionOp::funct:
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case InstructionOp::funct:
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FormatComment(dest, inst, pc, regs, s_special_table[static_cast<u8>(inst.r.funct.GetValue())]);
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FormatComment(dest, inst, pc, s_special_table[static_cast<u8>(inst.r.funct.GetValue())]);
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return;
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return;
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case InstructionOp::cop0:
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case InstructionOp::cop0:
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@ -576,8 +619,7 @@ void CPU::DisassembleInstructionComment(SmallStringBase* dest, u32 pc, u32 bits,
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{
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{
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if (inst.cop.IsCommonInstruction())
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if (inst.cop.IsCommonInstruction())
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{
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{
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FormatCopComment(dest, pc, regs, inst, s_cop_common_table.data(), s_cop_common_table.size(),
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FormatCopComment(dest, pc, inst, s_cop_common_table.data(), s_cop_common_table.size(), inst.cop.CommonOp());
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inst.cop.CommonOp());
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}
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}
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else
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else
|
||||||
{
|
{
|
||||||
|
@ -585,7 +627,7 @@ void CPU::DisassembleInstructionComment(SmallStringBase* dest, u32 pc, u32 bits,
|
||||||
{
|
{
|
||||||
case InstructionOp::cop0:
|
case InstructionOp::cop0:
|
||||||
{
|
{
|
||||||
FormatCopComment(dest, pc, regs, inst, s_cop0_table.data(), s_cop0_table.size(), inst.cop.Cop0Op());
|
FormatCopComment(dest, pc, inst, s_cop0_table.data(), s_cop0_table.size(), inst.cop.Cop0Op());
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
@ -612,14 +654,14 @@ void CPU::DisassembleInstructionComment(SmallStringBase* dest, u32 pc, u32 bits,
|
||||||
const bool bgez = ConvertToBoolUnchecked(rt & u8(1));
|
const bool bgez = ConvertToBoolUnchecked(rt & u8(1));
|
||||||
const bool link = ConvertToBoolUnchecked((rt >> 4) & u8(1));
|
const bool link = ConvertToBoolUnchecked((rt >> 4) & u8(1));
|
||||||
if (link)
|
if (link)
|
||||||
FormatComment(dest, inst, pc, regs, bgez ? "bgezal $rs, $rel" : "bltzal $rs, $rel");
|
FormatComment(dest, inst, pc, bgez ? "bgezal $rs, $rel" : "bltzal $rs, $rel");
|
||||||
else
|
else
|
||||||
FormatComment(dest, inst, pc, regs, bgez ? "bgez $rs, $rel" : "bltz $rs, $rel");
|
FormatComment(dest, inst, pc, bgez ? "bgez $rs, $rel" : "bltz $rs, $rel");
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
FormatComment(dest, inst, pc, regs, s_base_table[static_cast<u8>(inst.op.GetValue())]);
|
FormatComment(dest, inst, pc, s_base_table[static_cast<u8>(inst.op.GetValue())]);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -9,7 +9,7 @@ class SmallStringBase;
|
||||||
namespace CPU {
|
namespace CPU {
|
||||||
|
|
||||||
void DisassembleInstruction(SmallStringBase* dest, u32 pc, u32 bits);
|
void DisassembleInstruction(SmallStringBase* dest, u32 pc, u32 bits);
|
||||||
void DisassembleInstructionComment(SmallStringBase* dest, u32 pc, u32 bits, Registers* regs);
|
void DisassembleInstructionComment(SmallStringBase* dest, u32 pc, u32 bits);
|
||||||
|
|
||||||
const char* GetGTERegisterName(u32 index);
|
const char* GetGTERegisterName(u32 index);
|
||||||
|
|
||||||
|
|
|
@ -112,7 +112,7 @@ QVariant DebuggerCodeModel::data(const QModelIndex& index, int role /*= Qt::Disp
|
||||||
return tr("<invalid>");
|
return tr("<invalid>");
|
||||||
|
|
||||||
TinyString str;
|
TinyString str;
|
||||||
CPU::DisassembleInstructionComment(&str, address, instruction_bits, &CPU::g_state.regs);
|
CPU::DisassembleInstructionComment(&str, address, instruction_bits);
|
||||||
return QString::fromUtf8(str.c_str(), static_cast<int>(str.length()));
|
return QString::fromUtf8(str.c_str(), static_cast<int>(str.length()));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue