mirror of
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Core: Add constexpr MIPS Encoder
From https://raw.githubusercontent.com/grumpycoders/pcsx-redux/main/src/mips/common/util/encoder.hh
This commit is contained in:
Stenzek
parent
71738d12e0
commit
9e09f53566
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@ -2735,6 +2735,31 @@ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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SOFTWARE.
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</pre>
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</pre>
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<h3>MIPS Encoder - <a href="https://raw.githubusercontent.com/grumpycoders/pcsx-redux/main/src/mips/common/util/encoder.hh">https://raw.githubusercontent.com/grumpycoders/pcsx-redux/main/src/mips/common/util/encoder.hh</a></h3>
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<pre>
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MIT License
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Copyright (c) 2021 PCSX-Redux authors
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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</pre>
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Some shaders provided with the application are sourced from:
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Some shaders provided with the application are sourced from:
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<ul>
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<ul>
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<li><a href="https://github.com/Matsilagi/RSRetroArch/">https://github.com/Matsilagi/RSRetroArch/</a></li>
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<li><a href="https://github.com/Matsilagi/RSRetroArch/">https://github.com/Matsilagi/RSRetroArch/</a></li>
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@ -81,6 +81,7 @@ add_library(core
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memory_card.h
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memory_card.h
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memory_card_image.cpp
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memory_card_image.cpp
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memory_card_image.h
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memory_card_image.h
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mips_encoder.h
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multitap.cpp
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multitap.cpp
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multitap.h
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multitap.h
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negcon.cpp
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negcon.cpp
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227
src/core/mips_encoder.h
Normal file
227
src/core/mips_encoder.h
Normal file
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@ -0,0 +1,227 @@
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/*
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MIT License
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Copyright (c) 2021 PCSX-Redux authors
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Sourced from https://raw.githubusercontent.com/grumpycoders/pcsx-redux/main/src/mips/common/util/encoder.hh
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*/
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#pragma once
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#include <stdint.h>
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namespace Mips {
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namespace Encoder {
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// clang-format off
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enum class Reg {
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R0, AT, V0, V1, A0, A1, A2, A3, // 00 to 07
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T0, T1, T2, T3, T4, T5, T6, T7, // 08 to 0f
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S0, S1, S2, S3, S4, S5, S6, S7, // 10 to 17
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T8, T9, K0, K1, GP, SP, S8, RA, // 18 to 1f
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};
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// clang-format on
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constexpr uint32_t iclass(uint32_t v) { return v << 26; }
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constexpr uint32_t dstVal(Reg r) { return uint32_t(r) << 11; }
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constexpr uint32_t tgtVal(Reg r) { return uint32_t(r) << 16; }
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constexpr uint32_t srcVal(Reg r) { return uint32_t(r) << 21; }
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// ALU
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constexpr uint32_t add(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100000; }
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constexpr uint32_t addu(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100001; }
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constexpr uint32_t addi(Reg tgt, Reg src, int16_t value) {
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uint32_t v = value;
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v &= 0xffff;
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return iclass(0b001000) | srcVal(src) | tgtVal(tgt) | v;
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}
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constexpr uint32_t addiu(Reg tgt, Reg src, int16_t value) {
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uint32_t v = value;
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v &= 0xffff;
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return iclass(0b001001) | srcVal(src) | tgtVal(tgt) | v;
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}
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constexpr uint32_t andd(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100100; }
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constexpr uint32_t andi(Reg tgt, Reg src, uint16_t value) {
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return iclass(0b001100) | srcVal(src) | tgtVal(tgt) | value;
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}
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constexpr uint32_t lui(Reg tgt, uint16_t value) { return iclass(0b001111) | tgtVal(tgt) | value; }
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constexpr uint32_t nor(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100111; }
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constexpr uint32_t orr(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100101; }
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constexpr uint32_t ori(Reg tgt, Reg src, uint16_t value) {
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return iclass(0b001101) | srcVal(src) | tgtVal(tgt) | value;
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}
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constexpr uint32_t slt(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b101010; }
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constexpr uint32_t sltu(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b101011; }
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constexpr uint32_t slti(Reg tgt, Reg src, int16_t value) {
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uint32_t v = value;
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v &= 0xffff;
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return iclass(0b001010) | srcVal(src) | tgtVal(tgt) | v;
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}
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constexpr uint32_t sltiu(Reg tgt, Reg src, uint16_t value) {
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return iclass(0b001011) | srcVal(src) | tgtVal(tgt) | value;
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}
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constexpr uint32_t sub(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100010; }
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constexpr uint32_t subu(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100011; }
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constexpr uint32_t xorr(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100110; }
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constexpr uint32_t xori(Reg tgt, Reg src, uint16_t value) {
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return iclass(0b001110) | srcVal(src) | tgtVal(tgt) | value;
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}
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// shifts
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constexpr uint32_t sll(Reg dst, Reg tgt, uint16_t sa) { return dstVal(dst) | tgtVal(tgt) | (sa << 6) | 0b000000; }
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constexpr uint32_t sllv(Reg dst, Reg tgt, Reg src) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b000100; }
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constexpr uint32_t sra(Reg dst, Reg tgt, uint16_t sa) { return dstVal(dst) | tgtVal(tgt) | (sa << 6) | 0b000011; }
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constexpr uint32_t srav(Reg dst, Reg tgt, Reg src) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b000111; }
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constexpr uint32_t srl(Reg dst, Reg tgt, uint16_t sa) { return dstVal(dst) | tgtVal(tgt) | (sa << 6) | 0b000010; }
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constexpr uint32_t srlv(Reg dst, Reg tgt, Reg src) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b000110; }
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// mults
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constexpr uint32_t div(Reg src, Reg tgt) { return tgtVal(tgt) | srcVal(src) | 0b011010; }
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constexpr uint32_t divu(Reg src, Reg tgt) { return tgtVal(tgt) | srcVal(src) | 0b011011; }
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constexpr uint32_t mfhi(Reg dst) { return dstVal(dst) | 0b010000; }
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constexpr uint32_t mflo(Reg dst) { return dstVal(dst) | 0b010010; }
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constexpr uint32_t mthi(Reg dst) { return dstVal(dst) | 0b010001; }
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constexpr uint32_t mtlo(Reg dst) { return dstVal(dst) | 0b010011; }
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constexpr uint32_t mult(Reg src, Reg tgt) { return tgtVal(tgt) | srcVal(src) | 0b011000; }
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constexpr uint32_t multu(Reg src, Reg tgt) { return tgtVal(tgt) | srcVal(src) | 0b011001; }
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// branches
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constexpr uint32_t beq(Reg src, Reg tgt, int16_t offset) {
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uint32_t o = offset >> 2;
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o &= 0xffff;
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return iclass(0b000100) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t bgez(Reg src, int16_t offset) {
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uint32_t o = offset >> 2;
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o &= 0xffff;
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return iclass(0b000001) | tgtVal(Reg(0b00001)) | srcVal(src) | o;
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}
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constexpr uint32_t bgezal(Reg src, int16_t offset) {
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uint32_t o = offset >> 2;
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o &= 0xffff;
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return iclass(0b000001) | tgtVal(Reg(0b10001)) | srcVal(src) | o;
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}
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constexpr uint32_t bgtz(Reg src, int16_t offset) {
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uint32_t o = offset >> 2;
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o &= 0xffff;
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return iclass(0b000111) | tgtVal(Reg(0b00000)) | srcVal(src) | o;
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}
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constexpr uint32_t blez(Reg src, int16_t offset) {
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uint32_t o = offset >> 2;
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o &= 0xffff;
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return iclass(0b000110) | tgtVal(Reg(0b00000)) | srcVal(src) | o;
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}
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constexpr uint32_t bltz(Reg src, int16_t offset) {
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uint32_t o = offset >> 2;
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o &= 0xffff;
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return iclass(0b000001) | tgtVal(Reg(0b00000)) | srcVal(src) | o;
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}
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constexpr uint32_t bltzal(Reg src, int16_t offset) {
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uint32_t o = offset >> 2;
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o &= 0xffff;
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return iclass(0b000001) | tgtVal(Reg(0b10000)) | srcVal(src) | o;
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}
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constexpr uint32_t bne(Reg src, Reg tgt, int16_t offset) {
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uint32_t o = offset >> 2;
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o &= 0xffff;
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return iclass(0b000101) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t brk(uint32_t code) { return (code << 6) | 0b001101; }
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constexpr uint32_t j(uint32_t addr) { return iclass(0b000010) | ((addr >> 2) & 0x03ffffff); }
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constexpr uint32_t jal(uint32_t addr) { return iclass(0b000011) | ((addr >> 2) & 0x03ffffff); }
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constexpr uint32_t jalr(Reg src, Reg dst = Reg::RA) { return dstVal(dst) | srcVal(src) | 0b001001; }
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constexpr uint32_t jr(Reg src) { return srcVal(src) | 0b001000; }
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constexpr uint32_t syscall() { return 0b001100; }
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// memory
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constexpr uint32_t lb(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b100000) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t lbu(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b100100) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t lh(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b100001) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t lhu(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b100101) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t lw(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b100011) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t lwl(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b100010) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t lwr(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b100110) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t sb(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b101000) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t sh(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b101001) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t sw(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b101011) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t swl(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b101010) | tgtVal(tgt) | srcVal(src) | o;
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}
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constexpr uint32_t swr(Reg tgt, int16_t offset, Reg src) {
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uint32_t o = offset;
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o &= 0xffff;
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return iclass(0b101110) | tgtVal(tgt) | srcVal(src) | o;
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}
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// cop0
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constexpr uint32_t mfc0(Reg tgt, uint8_t dst) { return iclass(0b010000) | tgtVal(tgt) | (dst << 11); }
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constexpr uint32_t mtc0(Reg tgt, uint8_t dst) { return iclass(0b010000) | (4 << 21) | tgtVal(tgt) | (dst << 11); }
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constexpr uint32_t rfe() { return 0x42000010; }
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// pseudo
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constexpr uint32_t nop() { return 0; }
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} // namespace Encoder
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} // namespace Mips
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