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CPU: Force-inline some accessor functions
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@ -9,6 +9,7 @@
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class StateWrapper;
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class StateWrapper;
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class Bus;
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class Bus;
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class System;
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namespace CPU {
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namespace CPU {
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@ -41,19 +42,20 @@ public:
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void Execute();
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void Execute();
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const Registers& GetRegs() const { return m_regs; }
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ALWAYS_INLINE Bus* GetBus() const { return m_bus; }
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Registers& GetRegs() { return m_regs; }
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TickCount GetPendingTicks() const { return m_pending_ticks; }
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ALWAYS_INLINE const Registers& GetRegs() const { return m_regs; }
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void ResetPendingTicks() { m_pending_ticks = 0; }
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ALWAYS_INLINE Registers& GetRegs() { return m_regs; }
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void AddPendingTicks(TickCount ticks)
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ALWAYS_INLINE TickCount GetPendingTicks() const { return m_pending_ticks; }
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ALWAYS_INLINE void ResetPendingTicks() { m_pending_ticks = 0; }
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ALWAYS_INLINE void AddPendingTicks(TickCount ticks) { m_pending_ticks += ticks; }
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ALWAYS_INLINE void SetDowncount(TickCount downcount)
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{
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{
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m_pending_ticks += ticks;
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m_downcount = (downcount < m_downcount) ? downcount : m_downcount;
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m_downcount -= ticks;
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}
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}
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ALWAYS_INLINE void ResetDowncount() { m_downcount = MAX_SLICE_SIZE; }
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void SetDowncount(TickCount downcount) { m_downcount = (downcount < m_downcount) ? downcount : m_downcount; }
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void ResetDowncount() { m_downcount = MAX_SLICE_SIZE; }
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// Sets the PC and flushes the pipeline.
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// Sets the PC and flushes the pipeline.
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void SetPC(u32 new_pc);
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void SetPC(u32 new_pc);
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@ -88,8 +90,8 @@ private:
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bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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// state helpers
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// state helpers
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bool InUserMode() const { return m_cop0_regs.sr.KUc; }
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ALWAYS_INLINE bool InUserMode() const { return m_cop0_regs.sr.KUc; }
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bool InKernelMode() const { return !m_cop0_regs.sr.KUc; }
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ALWAYS_INLINE bool InKernelMode() const { return !m_cop0_regs.sr.KUc; }
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void DisassembleAndPrint(u32 addr);
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void DisassembleAndPrint(u32 addr);
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void DisassembleAndLog(u32 addr);
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void DisassembleAndLog(u32 addr);
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@ -164,6 +166,7 @@ private:
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u32 m_next_load_delay_value = 0;
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u32 m_next_load_delay_value = 0;
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u32 m_cache_control = 0;
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u32 m_cache_control = 0;
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System* m_system = nullptr;
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// data cache (used as scratchpad)
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// data cache (used as scratchpad)
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std::array<u8, DCACHE_SIZE> m_dcache = {};
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std::array<u8, DCACHE_SIZE> m_dcache = {};
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