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CPU: Delay interrupts if the instruction in the pipeline is a TE instruction

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This commit is contained in:
Connor McLaughlin 2019-09-27 23:43:52 +10:00
parent e8cd174732
commit a479d820d4
2 changed files with 10 additions and 0 deletions
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5
src/pse/cpu_core.cpp
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@ -251,6 +251,11 @@ void Core::ClearExternalInterrupt(u8 bit)
bool Core::DispatchInterrupts() bool Core::DispatchInterrupts()
{ {
// If the instruction we're about to execute is a GTE instruction, delay dispatching the interrupt until the next
// instruction. For some reason, if we don't do this, we end up with incorrectly sorted polygons and flickering..
if (m_next_instruction.IsCop2Instruction())
return false;
// const bool do_interrupt = m_cop0_regs.sr.IEc && ((m_cop0_regs.cause.Ip & m_cop0_regs.sr.Im) != 0); // const bool do_interrupt = m_cop0_regs.sr.IEc && ((m_cop0_regs.cause.Ip & m_cop0_regs.sr.Im) != 0);
const bool do_interrupt = const bool do_interrupt =
m_cop0_regs.sr.IEc && (((m_cop0_regs.cause.bits & m_cop0_regs.sr.bits) & (UINT32_C(0xFF) << 8)) != 0); m_cop0_regs.sr.IEc && (((m_cop0_regs.cause.bits & m_cop0_regs.sr.bits) & (UINT32_C(0xFF) << 8)) != 0);

5
src/pse/cpu_types.h
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@ -182,6 +182,11 @@ union Instruction
Cop0Instruction Cop0Op() const { return static_cast<Cop0Instruction>(bits & UINT32_C(0x3F)); } Cop0Instruction Cop0Op() const { return static_cast<Cop0Instruction>(bits & UINT32_C(0x3F)); }
} cop; } cop;
bool IsCop2Instruction() const
{
return (op == InstructionOp::cop2 || op == InstructionOp::lwc2 || op == InstructionOp::swc2);
}
}; };
struct Registers struct Registers