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https://github.com/RetroDECK/Duckstation.git
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CPU/Recompiler: Implement PGXP CPU mode
This commit is contained in:
Connor McLaughlin
parent
0bfa1bf873
commit
bc021ddfd9
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@ -1140,6 +1140,9 @@ bool CodeGenerator::Compile_Bitwise(const CodeBlockInstruction& cbi)
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result = OrValues(lhs, rhs);
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if (spec_lhs && spec_rhs)
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spec_value = *spec_lhs | *spec_rhs;
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_ORI, Value::FromConstantU32(cbi.instruction.bits), result, lhs);
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}
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break;
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@ -1148,6 +1151,9 @@ bool CodeGenerator::Compile_Bitwise(const CodeBlockInstruction& cbi)
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result = AndValues(lhs, rhs);
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if (spec_lhs && spec_rhs)
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spec_value = *spec_lhs & *spec_rhs;
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_ANDI, Value::FromConstantU32(cbi.instruction.bits), result, lhs);
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}
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break;
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@ -1156,6 +1162,9 @@ bool CodeGenerator::Compile_Bitwise(const CodeBlockInstruction& cbi)
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result = XorValues(lhs, rhs);
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if (spec_lhs && spec_rhs)
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spec_value = *spec_lhs ^ *spec_rhs;
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_XORI, Value::FromConstantU32(cbi.instruction.bits), result, lhs);
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}
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break;
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@ -1168,6 +1177,9 @@ bool CodeGenerator::Compile_Bitwise(const CodeBlockInstruction& cbi)
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result = OrValues(lhs, rhs);
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if (spec_lhs && spec_rhs)
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spec_value = *spec_lhs | *spec_rhs;
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_OR_, Value::FromConstantU32(cbi.instruction.bits), result, lhs, rhs);
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}
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break;
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@ -1176,6 +1188,9 @@ bool CodeGenerator::Compile_Bitwise(const CodeBlockInstruction& cbi)
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result = AndValues(lhs, rhs);
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if (spec_lhs && spec_rhs)
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spec_value = *spec_lhs & *spec_rhs;
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_AND_, Value::FromConstantU32(cbi.instruction.bits), result, lhs, rhs);
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}
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break;
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@ -1184,6 +1199,9 @@ bool CodeGenerator::Compile_Bitwise(const CodeBlockInstruction& cbi)
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result = XorValues(lhs, rhs);
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if (spec_lhs && spec_rhs)
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spec_value = *spec_lhs ^ *spec_rhs;
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_XOR_, Value::FromConstantU32(cbi.instruction.bits), result, lhs, rhs);
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}
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break;
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@ -1192,6 +1210,9 @@ bool CodeGenerator::Compile_Bitwise(const CodeBlockInstruction& cbi)
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result = NotValue(OrValues(lhs, rhs));
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if (spec_lhs && spec_rhs)
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spec_value = ~(*spec_lhs | *spec_rhs);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_NOR, Value::FromConstantU32(cbi.instruction.bits), result, lhs, rhs);
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}
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break;
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@ -1246,6 +1267,14 @@ bool CodeGenerator::Compile_Shift(const CodeBlockInstruction& cbi)
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result = ShlValues(rt, shamt, false);
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if (rt_spec && shamt_spec)
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result_spec = *rt_spec << *shamt_spec;
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if (g_settings.UsingPGXPCPUMode())
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{
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if (cbi.instruction.r.funct == InstructionFunct::sll)
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EmitFunctionCall(nullptr, &PGXP::CPU_SLL, Value::FromConstantU32(cbi.instruction.bits), result, rt);
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else // if (cbi.instruction.r.funct == InstructionFunct::sllv)
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EmitFunctionCall(nullptr, &PGXP::CPU_SLLV, Value::FromConstantU32(cbi.instruction.bits), result, rt, shamt);
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}
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}
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break;
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@ -1255,6 +1284,14 @@ bool CodeGenerator::Compile_Shift(const CodeBlockInstruction& cbi)
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result = ShrValues(rt, shamt, false);
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if (rt_spec && shamt_spec)
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result_spec = *rt_spec >> *shamt_spec;
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if (g_settings.UsingPGXPCPUMode())
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{
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if (cbi.instruction.r.funct == InstructionFunct::srl)
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EmitFunctionCall(nullptr, &PGXP::CPU_SRL, Value::FromConstantU32(cbi.instruction.bits), result, rt);
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else // if (cbi.instruction.r.funct == InstructionFunct::srlv)
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EmitFunctionCall(nullptr, &PGXP::CPU_SRLV, Value::FromConstantU32(cbi.instruction.bits), result, rt, shamt);
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}
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}
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break;
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@ -1264,6 +1301,14 @@ bool CodeGenerator::Compile_Shift(const CodeBlockInstruction& cbi)
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result = SarValues(rt, shamt, false);
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if (rt_spec && shamt_spec)
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result_spec = static_cast<u32>(static_cast<s32>(*rt_spec) << *shamt_spec);
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if (g_settings.UsingPGXPCPUMode())
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{
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if (cbi.instruction.r.funct == InstructionFunct::sra)
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EmitFunctionCall(nullptr, &PGXP::CPU_SRA, Value::FromConstantU32(cbi.instruction.bits), result, rt);
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else // if (cbi.instruction.r.funct == InstructionFunct::srav)
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EmitFunctionCall(nullptr, &PGXP::CPU_SRAV, Value::FromConstantU32(cbi.instruction.bits), result, rt, shamt);
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}
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}
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break;
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@ -1579,22 +1624,46 @@ bool CodeGenerator::Compile_MoveHiLo(const CodeBlockInstruction& cbi)
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switch (cbi.instruction.r.funct)
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{
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case InstructionFunct::mfhi:
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m_register_cache.WriteGuestRegister(cbi.instruction.r.rd, m_register_cache.ReadGuestRegister(Reg::hi));
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{
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Value hi = m_register_cache.ReadGuestRegister(Reg::hi);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_MFHI, Value::FromConstantU32(cbi.instruction.bits), hi);
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m_register_cache.WriteGuestRegister(cbi.instruction.r.rd, std::move(hi));
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SpeculativeWriteReg(cbi.instruction.r.rd, std::nullopt);
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break;
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}
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break;
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case InstructionFunct::mthi:
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m_register_cache.WriteGuestRegister(Reg::hi, m_register_cache.ReadGuestRegister(cbi.instruction.r.rs));
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break;
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{
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Value rs = m_register_cache.ReadGuestRegister(cbi.instruction.r.rs);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_MTHI, Value::FromConstantU32(cbi.instruction.bits), rs);
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m_register_cache.WriteGuestRegister(Reg::hi, std::move(rs));
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}
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break;
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case InstructionFunct::mflo:
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m_register_cache.WriteGuestRegister(cbi.instruction.r.rd, m_register_cache.ReadGuestRegister(Reg::lo));
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{
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Value lo = m_register_cache.ReadGuestRegister(Reg::lo);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_MFLO, Value::FromConstantU32(cbi.instruction.bits), lo);
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m_register_cache.WriteGuestRegister(cbi.instruction.r.rd, std::move(lo));
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SpeculativeWriteReg(cbi.instruction.r.rd, std::nullopt);
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break;
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}
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break;
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case InstructionFunct::mtlo:
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m_register_cache.WriteGuestRegister(Reg::lo, m_register_cache.ReadGuestRegister(cbi.instruction.r.rs));
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break;
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{
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Value rs = m_register_cache.ReadGuestRegister(cbi.instruction.r.rs);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_MTLO, Value::FromConstantU32(cbi.instruction.bits), rs);
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m_register_cache.WriteGuestRegister(Reg::lo, std::move(rs));
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}
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break;
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default:
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UnreachableCode();
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@ -1652,16 +1721,32 @@ bool CodeGenerator::Compile_Add(const CodeBlockInstruction& cbi)
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}
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// detect register moves and handle them for pgxp
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bool do_pgxp_cpu = g_settings.UsingPGXPCPUMode();
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if (g_settings.gpu_pgxp_enable && rhs.HasConstantValue(0))
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{
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EmitFunctionCall(nullptr, &PGXP::CPU_MOVE,
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Value::FromConstantU32((static_cast<u32>(dest) << 8) | (static_cast<u32>(lhs_src))), lhs);
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do_pgxp_cpu = false;
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}
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Value result = AddValues(lhs, rhs, check_overflow);
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if (check_overflow)
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GenerateExceptionExit(cbi, Exception::Ov, Condition::Overflow);
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if (do_pgxp_cpu)
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{
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if (cbi.instruction.op != InstructionOp::funct)
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{
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// addiu/addiu
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EmitFunctionCall(nullptr, &PGXP::CPU_ADDI, Value::FromConstantU32(cbi.instruction.bits), result, lhs);
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}
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else
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{
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// add/addu
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EmitFunctionCall(nullptr, &PGXP::CPU_ADD, Value::FromConstantU32(cbi.instruction.bits), result, lhs, rhs);
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}
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}
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m_register_cache.WriteGuestRegister(dest, std::move(result));
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SpeculativeValue value_spec;
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@ -1690,6 +1775,9 @@ bool CodeGenerator::Compile_Subtract(const CodeBlockInstruction& cbi)
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if (check_overflow)
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GenerateExceptionExit(cbi, Exception::Ov, Condition::Overflow);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_SUB, Value::FromConstantU32(cbi.instruction.bits), result, lhs, rhs);
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m_register_cache.WriteGuestRegister(cbi.instruction.r.rd, std::move(result));
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SpeculativeValue value_spec;
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@ -1706,8 +1794,14 @@ bool CodeGenerator::Compile_Multiply(const CodeBlockInstruction& cbi)
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InstructionPrologue(cbi, 1);
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const bool signed_multiply = (cbi.instruction.r.funct == InstructionFunct::mult);
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std::pair<Value, Value> result = MulValues(m_register_cache.ReadGuestRegister(cbi.instruction.r.rs),
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m_register_cache.ReadGuestRegister(cbi.instruction.r.rt), signed_multiply);
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Value rs = m_register_cache.ReadGuestRegister(cbi.instruction.r.rs);
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Value rt = m_register_cache.ReadGuestRegister(cbi.instruction.r.rt);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, signed_multiply ? &PGXP::CPU_MULT : &PGXP::CPU_MULTU, rs, rt);
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std::pair<Value, Value> result = MulValues(rs, rt, signed_multiply);
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rs.ReleaseAndClear();
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rt.ReleaseAndClear();
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m_register_cache.WriteGuestRegister(Reg::hi, std::move(result.first));
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m_register_cache.WriteGuestRegister(Reg::lo, std::move(result.second));
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@ -1764,6 +1858,10 @@ bool CodeGenerator::Compile_Divide(const CodeBlockInstruction& cbi)
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Value num = m_register_cache.ReadGuestRegister(cbi.instruction.r.rs);
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Value denom = m_register_cache.ReadGuestRegister(cbi.instruction.r.rt);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_DIV, num, denom);
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if (num.IsConstant() && denom.IsConstant())
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{
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const auto [lo, hi] = MIPSDivide(static_cast<u32>(num.constant_value), static_cast<u32>(denom.constant_value));
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@ -1821,6 +1919,10 @@ bool CodeGenerator::Compile_SignedDivide(const CodeBlockInstruction& cbi)
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Value num = m_register_cache.ReadGuestRegister(cbi.instruction.r.rs);
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Value denom = m_register_cache.ReadGuestRegister(cbi.instruction.r.rt);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_DIVU, num, denom);
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if (num.IsConstant() && denom.IsConstant())
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{
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const auto [lo, hi] = MIPSDivide(num.GetS32ConstantValue(), denom.GetS32ConstantValue());
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@ -1938,6 +2040,19 @@ bool CodeGenerator::Compile_SetLess(const CodeBlockInstruction& cbi)
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Value result = m_register_cache.AllocateScratch(RegSize_32);
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EmitCmp(lhs.host_reg, rhs);
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EmitSetConditionResult(result.host_reg, result.size, signed_comparison ? Condition::Less : Condition::Below);
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if (g_settings.UsingPGXPCPUMode())
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{
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if (cbi.instruction.op == InstructionOp::slti)
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EmitFunctionCall(nullptr, &PGXP::CPU_SLTI, Value::FromConstantU32(cbi.instruction.bits), result, lhs);
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else if (cbi.instruction.op == InstructionOp::sltiu)
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EmitFunctionCall(nullptr, &PGXP::CPU_SLTIU, Value::FromConstantU32(cbi.instruction.bits), result, lhs);
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else if (cbi.instruction.r.funct == InstructionFunct::slt)
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EmitFunctionCall(nullptr, &PGXP::CPU_SLT, Value::FromConstantU32(cbi.instruction.bits), result, lhs, rhs);
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else // if (cbi.instruction.r.funct == InstructionFunct::sltu)
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EmitFunctionCall(nullptr, &PGXP::CPU_SLTU, Value::FromConstantU32(cbi.instruction.bits), result, lhs, rhs);
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}
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m_register_cache.WriteGuestRegister(dest, std::move(result));
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SpeculativeValue value_spec;
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@ -2161,6 +2276,14 @@ bool CodeGenerator::Compile_lui(const CodeBlockInstruction& cbi)
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// rt <- (imm << 16)
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const u32 value = cbi.instruction.i.imm_zext32() << 16;
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if (g_settings.UsingPGXPCPUMode())
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{
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// TODO: rtVal can be skipped here, and probably worthwhile given this is a common instruction.
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EmitFunctionCall(nullptr, &PGXP::CPU_LUI, Value::FromConstantU32(cbi.instruction.bits),
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Value::FromConstantU32(value));
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}
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m_register_cache.WriteGuestRegister(cbi.instruction.i.rt, Value::FromConstantU32(value));
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SpeculativeWriteReg(cbi.instruction.i.rt, value);
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@ -2245,6 +2368,10 @@ bool CodeGenerator::Compile_cop0(const CodeBlockInstruction& cbi)
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// coprocessor loads are load-delayed
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Value value = m_register_cache.AllocateScratch(RegSize_32);
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EmitLoadCPUStructField(value.host_reg, value.size, offset);
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_MFC0, Value::FromConstantU32(cbi.instruction.bits), value);
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m_register_cache.WriteGuestRegisterDelayed(cbi.instruction.r.rt, std::move(value));
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SpeculativeWriteReg(cbi.instruction.r.rt, std::nullopt);
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}
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@ -2257,7 +2384,18 @@ bool CodeGenerator::Compile_cop0(const CodeBlockInstruction& cbi)
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if (write_mask != UINT32_C(0xFFFFFFFF))
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{
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// need to adjust the mask
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value = AndValues(value, Value::FromConstantU32(write_mask));
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Value masked_value = AndValues(value, Value::FromConstantU32(write_mask));
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if (g_settings.UsingPGXPCPUMode())
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{
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EmitFunctionCall(nullptr, &PGXP::CPU_MTC0, Value::FromConstantU32(cbi.instruction.bits), masked_value,
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value);
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}
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value = std::move(masked_value);
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}
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else
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{
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if (g_settings.UsingPGXPCPUMode())
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EmitFunctionCall(nullptr, &PGXP::CPU_MTC0, Value::FromConstantU32(cbi.instruction.bits), value, value);
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}
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// changing SR[Isc] needs to update fastmem views
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@ -650,17 +650,6 @@ void HostInterface::FixIncompatibleSettings(bool display_osd_messages)
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}
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g_settings.gpu_pgxp_enable = false;
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}
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else if (g_settings.gpu_pgxp_cpu && g_settings.cpu_execution_mode == CPUExecutionMode::Recompiler)
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{
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if (display_osd_messages)
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{
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AddOSDMessage(
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TranslateStdString("OSDMessage",
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"PGXP CPU mode is incompatible with the recompiler, using Cached Interpreter instead."),
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10.0f);
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}
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g_settings.cpu_execution_mode = CPUExecutionMode::CachedInterpreter;
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}
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}
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#ifndef WITH_MMAP_FASTMEM
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@ -804,7 +793,8 @@ void HostInterface::CheckForSettingsChanges(const Settings& old_settings)
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}
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if (g_settings.gpu_pgxp_enable != old_settings.gpu_pgxp_enable ||
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(g_settings.gpu_pgxp_enable && g_settings.gpu_pgxp_culling != old_settings.gpu_pgxp_culling))
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(g_settings.gpu_pgxp_enable && (g_settings.gpu_pgxp_culling != old_settings.gpu_pgxp_culling ||
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g_settings.gpu_pgxp_cpu != old_settings.gpu_pgxp_cpu)))
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{
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if (g_settings.IsUsingCodeCache())
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{
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@ -233,6 +233,7 @@ struct Settings
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}
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ALWAYS_INLINE bool UsingPGXPDepthBuffer() const { return gpu_pgxp_enable && gpu_pgxp_depth_buffer; }
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ALWAYS_INLINE bool UsingPGXPCPUMode() const { return gpu_pgxp_enable && gpu_pgxp_cpu; }
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ALWAYS_INLINE float GetPGXPDepthClearThreshold() const { return gpu_pgxp_depth_clear_threshold * 4096.0f; }
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ALWAYS_INLINE void SetPGXPDepthClearThreshold(float value) { gpu_pgxp_depth_clear_threshold = value / 4096.0f; }
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