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CPU: Inline instruction accessor functions
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1adb1d14ae
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@ -151,8 +151,8 @@ union Instruction
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BitField<u32, Reg, 16, 5> rt;
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BitField<u32, Reg, 16, 5> rt;
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BitField<u32, u16, 0, 16> imm;
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BitField<u32, u16, 0, 16> imm;
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u32 imm_sext32() const { return SignExtend32(imm.GetValue()); }
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ALWAYS_INLINE u32 imm_sext32() const { return SignExtend32(imm.GetValue()); }
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u32 imm_zext32() const { return ZeroExtend32(imm.GetValue()); }
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ALWAYS_INLINE u32 imm_zext32() const { return ZeroExtend32(imm.GetValue()); }
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} i;
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} i;
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union
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union
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@ -176,11 +176,14 @@ union Instruction
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BitField<u32, u16, 0, 16> imm16;
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BitField<u32, u16, 0, 16> imm16;
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BitField<u32, u32, 0, 25> imm25;
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BitField<u32, u32, 0, 25> imm25;
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bool IsCommonInstruction() const { return (bits & (UINT32_C(1) << 25)) == 0; }
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ALWAYS_INLINE bool IsCommonInstruction() const { return (bits & (UINT32_C(1) << 25)) == 0; }
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CopCommonInstruction CommonOp() const { return static_cast<CopCommonInstruction>((bits >> 21) & UINT32_C(0b1111)); }
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ALWAYS_INLINE CopCommonInstruction CommonOp() const
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{
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return static_cast<CopCommonInstruction>((bits >> 21) & UINT32_C(0b1111));
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}
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Cop0Instruction Cop0Op() const { return static_cast<Cop0Instruction>(bits & UINT32_C(0x3F)); }
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ALWAYS_INLINE Cop0Instruction Cop0Op() const { return static_cast<Cop0Instruction>(bits & UINT32_C(0x3F)); }
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} cop;
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} cop;
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bool IsCop2Instruction() const
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bool IsCop2Instruction() const
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@ -274,7 +277,7 @@ struct Cop0Registers
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{
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{
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u32 BPC; // breakpoint on execute
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u32 BPC; // breakpoint on execute
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u32 BDA; // breakpoint on data access
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u32 BDA; // breakpoint on data access
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u32 TAR; // randomly memorized jump address
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u32 TAR; // randomly memorized jump address
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u32 BadVaddr; // bad virtual address value
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u32 BadVaddr; // bad virtual address value
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u32 BDAM; // data breakpoint mask
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u32 BDAM; // data breakpoint mask
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u32 BPCM; // execute breakpoint mask
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u32 BPCM; // execute breakpoint mask
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@ -34,10 +34,10 @@ union FLAGS
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static constexpr u32 WRITE_MASK = UINT32_C(0xFFFFF000);
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static constexpr u32 WRITE_MASK = UINT32_C(0xFFFFF000);
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void Clear() { bits = 0; }
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ALWAYS_INLINE void Clear() { bits = 0; }
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// Bits 30..23, 18..13 OR'ed
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// Bits 30..23, 18..13 OR'ed
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void UpdateError() { error = (bits & UINT32_C(0x7F87E000)) != UINT32_C(0); }
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ALWAYS_INLINE void UpdateError() { error = (bits & UINT32_C(0x7F87E000)) != UINT32_C(0); }
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};
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};
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union Regs
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union Regs
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@ -130,7 +130,7 @@ union Instruction
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BitField<u32, bool, 10, 1> lm; // saturate IR1, IR2, IR3 result
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BitField<u32, bool, 10, 1> lm; // saturate IR1, IR2, IR3 result
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BitField<u32, u8, 0, 6> command;
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BitField<u32, u8, 0, 6> command;
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u8 GetShift() const { return sf ? 12 : 0; }
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ALWAYS_INLINE u8 GetShift() const { return sf ? 12 : 0; }
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};
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};
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} // namespace GTE
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} // namespace GTE
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