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CPU: Inline instruction accessor functions

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This commit is contained in:
Connor McLaughlin 2019-10-26 15:44:03 +10:00
parent 1adb1d14ae
commit bedc305b64
2 changed files with 12 additions and 9 deletions
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13
src/core/cpu_types.h
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@ -151,8 +151,8 @@ union Instruction
BitField<u32, Reg, 16, 5> rt;
BitField<u32, u16, 0, 16> imm;
u32 imm_sext32() const { return SignExtend32(imm.GetValue()); }
u32 imm_zext32() const { return ZeroExtend32(imm.GetValue()); }
ALWAYS_INLINE u32 imm_sext32() const { return SignExtend32(imm.GetValue()); }
ALWAYS_INLINE u32 imm_zext32() const { return ZeroExtend32(imm.GetValue()); }
} i;
union
@ -176,11 +176,14 @@ union Instruction
BitField<u32, u16, 0, 16> imm16;
BitField<u32, u32, 0, 25> imm25;
bool IsCommonInstruction() const { return (bits & (UINT32_C(1) << 25)) == 0; }
ALWAYS_INLINE bool IsCommonInstruction() const { return (bits & (UINT32_C(1) << 25)) == 0; }
CopCommonInstruction CommonOp() const { return static_cast<CopCommonInstruction>((bits >> 21) & UINT32_C(0b1111)); }
ALWAYS_INLINE CopCommonInstruction CommonOp() const
{
return static_cast<CopCommonInstruction>((bits >> 21) & UINT32_C(0b1111));
}
Cop0Instruction Cop0Op() const { return static_cast<Cop0Instruction>(bits & UINT32_C(0x3F)); }
ALWAYS_INLINE Cop0Instruction Cop0Op() const { return static_cast<Cop0Instruction>(bits & UINT32_C(0x3F)); }
} cop;
bool IsCop2Instruction() const

6
src/core/gte_types.h
View file

@ -34,10 +34,10 @@ union FLAGS
static constexpr u32 WRITE_MASK = UINT32_C(0xFFFFF000);
void Clear() { bits = 0; }
ALWAYS_INLINE void Clear() { bits = 0; }
// Bits 30..23, 18..13 OR'ed
void UpdateError() { error = (bits & UINT32_C(0x7F87E000)) != UINT32_C(0); }
ALWAYS_INLINE void UpdateError() { error = (bits & UINT32_C(0x7F87E000)) != UINT32_C(0); }
};
union Regs
@ -130,7 +130,7 @@ union Instruction
BitField<u32, bool, 10, 1> lm; // saturate IR1, IR2, IR3 result
BitField<u32, u8, 0, 6> command;
u8 GetShift() const { return sf ? 12 : 0; }
ALWAYS_INLINE u8 GetShift() const { return sf ? 12 : 0; }
};
} // namespace GTE