From c2a08bdb1d6358ebfe4f88ba1d9bfbeebd34de29 Mon Sep 17 00:00:00 2001
From: Stenzek <stenzek@gmail.com>
Date: Tue, 2 Apr 2024 00:27:39 +1000
Subject: [PATCH] CPU/NewRec: Fix ARM32 (again)
---
src/core/cpu_newrec_compiler_aarch32.cpp | 8 ++++----
src/core/cpu_recompiler_types.h | 1 -
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/core/cpu_newrec_compiler_aarch32.cpp b/src/core/cpu_newrec_compiler_aarch32.cpp
index a15eef73a..3d4d8a86d 100644
--- a/src/core/cpu_newrec_compiler_aarch32.cpp
+++ b/src/core/cpu_newrec_compiler_aarch32.cpp
@@ -1588,7 +1588,7 @@ void CPU::NewRec::AArch32Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
// We'd need to be careful here if we weren't overwriting it..
ComputeLoadStoreAddressArg(cf, address, addr);
- armAsm->and_(RARG1, addr, armCheckLogicalConstant(~0x3u));
+ armAsm->bic(RARG1, addr, 3);
GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; });
if (inst->r.rt == Reg::zero)
@@ -1660,7 +1660,7 @@ void CPU::NewRec::AArch32Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
{
Flush(FLUSH_FOR_C_CALL);
armAsm->mov(RARG3, value);
- armAsm->and_(RARG2, addr, armCheckLogicalConstant(~0x3u));
+ armAsm->bic(RARG2, addr, 3);
EmitMov(RARG1, inst->bits);
EmitCall(reinterpret_cast<const void*>(&PGXP::CPU_LW));
}
@@ -1797,12 +1797,12 @@ void CPU::NewRec::AArch32Compiler::Compile_swx(CompileFlags cf, MemoryAccessSize
// TODO: if address is constant, this can be simplified..
// We'd need to be careful here if we weren't overwriting it..
ComputeLoadStoreAddressArg(cf, address, addr);
- armAsm->and_(RARG1, addr, armCheckLogicalConstant(~0x3u));
+ armAsm->bic(RARG1, addr, 3);
GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; });
armAsm->and_(RSCRATCH, addr, 3);
armAsm->lsl(RSCRATCH, RSCRATCH, 3); // *8
- armAsm->and_(addr, addr, armCheckLogicalConstant(~0x3u));
+ armAsm->bic(addr, addr, 3);
// Need to load down here for PGXP-off, because it's in a volatile reg that can get overwritten by flush.
if (!g_settings.gpu_pgxp_enable)
diff --git a/src/core/cpu_recompiler_types.h b/src/core/cpu_recompiler_types.h
index 3dd420a81..d15175a84 100644
--- a/src/core/cpu_recompiler_types.h
+++ b/src/core/cpu_recompiler_types.h
@@ -82,7 +82,6 @@ constexpr u32 MAX_FAR_HOST_BYTES_PER_INSTRUCTION = 128;
#define RARG1 vixl::aarch32::r0
#define RARG2 vixl::aarch32::r1
#define RARG3 vixl::aarch32::r2
-#define RARG4 vixl::aarch32::r3
#define RSCRATCH vixl::aarch32::r12
#define RSTATE vixl::aarch32::r4