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SPU: Drop OOB register warnings to dev level
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83a031e22f
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@ -300,7 +300,7 @@ u16 SPU::ReadRegister(u32 offset)
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return m_voices[voice_index].right_volume.current_level;
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return m_voices[voice_index].right_volume.current_level;
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}
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}
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Log_ErrorPrintf("Unknown SPU register read: offset 0x%X (address 0x%08X)", offset, offset | SPU_BASE);
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Log_DevPrintf("Unknown SPU register read: offset 0x%X (address 0x%08X)", offset, offset | SPU_BASE);
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return UINT16_C(0xFFFF);
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return UINT16_C(0xFFFF);
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}
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}
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}
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}
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@ -584,8 +584,8 @@ void SPU::WriteRegister(u32 offset, u16 value)
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return;
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return;
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}
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}
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Log_ErrorPrintf("Unknown SPU register write: offset 0x%X (address 0x%08X) value 0x%04X", offset,
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Log_DevPrintf("Unknown SPU register write: offset 0x%X (address 0x%08X) value 0x%04X", offset, offset | SPU_BASE,
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offset | SPU_BASE, ZeroExtend32(value));
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ZeroExtend32(value));
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return;
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return;
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}
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}
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}
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}
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@ -1804,10 +1804,6 @@ bool SetExpansionROM(const char* filename)
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void StallCPU(TickCount ticks)
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void StallCPU(TickCount ticks)
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{
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{
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CPU::AddPendingTicks(ticks);
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CPU::AddPendingTicks(ticks);
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#if 0
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if (CPU::GetPendingTicks() >= CPU::GetDowncount() && !m_running_events)
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RunEvents();
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#endif
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}
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}
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Controller* GetController(u32 slot)
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Controller* GetController(u32 slot)
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