From ced3038e732be21e4bbaa11bc7dbd1d8111ae91b Mon Sep 17 00:00:00 2001
From: Connor McLaughlin <mclaughc@outlook.com>
Date: Sat, 14 Sep 2019 13:39:36 +1000
Subject: [PATCH] CPU: Implement sub instruction

---
 src/pse/cpu_core.cpp | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/pse/cpu_core.cpp b/src/pse/cpu_core.cpp
index 35413615c..7d660e142 100644
--- a/src/pse/cpu_core.cpp
+++ b/src/pse/cpu_core.cpp
@@ -206,6 +206,11 @@ static constexpr bool AddOverflow(u32 old_value, u32 add_value, u32 new_value)
   return (((new_value ^ old_value) & (new_value ^ add_value)) & UINT32_C(0x80000000)) != 0;
 }
 
+static constexpr bool SubOverflow(u32 old_value, u32 sub_value, u32 new_value)
+{
+  return (((new_value ^ old_value) & (old_value ^ sub_value)) & UINT32_C(0x80000000)) != 0;
+}
+
 void Core::DisassembleAndPrint(u32 addr)
 {
   u32 bits;
@@ -358,6 +363,21 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
         }
         break;
 
+        case InstructionFunct::sub:
+        {
+          const u32 old_value = ReadReg(inst.r.rs);
+          const u32 sub_value = ReadReg(inst.r.rt);
+          const u32 new_value = old_value - sub_value;
+          if (SubOverflow(old_value, sub_value, new_value))
+          {
+            RaiseException(inst_pc, Exception::Ov);
+            return;
+          }
+
+          WriteReg(inst.r.rd, new_value);
+        }
+        break;
+
         case InstructionFunct::subu:
         {
           const u32 new_value = ReadReg(inst.r.rs) - ReadReg(inst.r.rt);