diff --git a/src/core/cpu_disasm.cpp b/src/core/cpu_disasm.cpp
index f9abf0a9a..90e14240f 100644
--- a/src/core/cpu_disasm.cpp
+++ b/src/core/cpu_disasm.cpp
@@ -434,8 +434,35 @@ void CPU::FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, c
     else if (std::strncmp(str, "offsetrs", 8) == 0)
     {
       const s32 offset = static_cast<s32>(inst.i.imm_sext32());
-      dest->append_format("{}addr={:08X}", dest->empty() ? "" : ", ",
-                          regs->r[static_cast<u8>(inst.i.rs.GetValue())] + offset);
+      const VirtualMemoryAddress address = (regs->r[static_cast<u8>(inst.i.rs.GetValue())] + offset);
+
+      if (!dest->empty())
+        dest->append_format(", ");
+
+      if (inst.op == InstructionOp::lb || inst.op == InstructionOp::lbu)
+      {
+        u8 data = 0;
+        CPU::SafeReadMemoryByte(address, &data);
+        dest->append_format("addr={:08X}[{:02X}]", address, data);
+      }
+      else if (inst.op == InstructionOp::lh || inst.op == InstructionOp::lhu)
+      {
+        u16 data = 0;
+        CPU::SafeReadMemoryHalfWord(address, &data);
+        dest->append_format("addr={:08X}[{:04X}]", address, data);
+      }
+      else if (inst.op == InstructionOp::lw || (inst.op >= InstructionOp::lwc0 && inst.op <= InstructionOp::lwc3) ||
+               inst.op == InstructionOp::lwl || inst.op == InstructionOp::lwr)
+      {
+        u32 data = 0;
+        CPU::SafeReadMemoryWord(address, &data);
+        dest->append_format("addr={:08X}[{:08X}]", address, data);
+      }
+      else
+      {
+        dest->append_format("addr={:08X}", address);
+      }
+
       str += 8;
     }
     else if (std::strncmp(str, "jt", 2) == 0)