From d58dbe04c080282bd9e657ae96de6806c6b206dc Mon Sep 17 00:00:00 2001
From: Connor McLaughlin <mclaughc@outlook.com>
Date: Sun, 15 Sep 2019 12:16:51 +1000
Subject: [PATCH] CPU: Fix load delay register reads for same register in delay
 slot

---
 src/pse/cpu_core.cpp | 11 ++++++++---
 src/pse/cpu_core.h   |  3 +++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/pse/cpu_core.cpp b/src/pse/cpu_core.cpp
index 2eec84a61..d17c180b0 100644
--- a/src/pse/cpu_core.cpp
+++ b/src/pse/cpu_core.cpp
@@ -179,13 +179,18 @@ void Core::RaiseException(Exception excode)
   FlushPipeline();
 }
 
-void Core::FlushPipeline()
+void Core::FlushLoadDelay()
 {
-  // loads are flushed
   m_load_delay_reg = Reg::count;
   m_load_delay_old_value = 0;
   m_next_load_delay_reg = Reg::count;
   m_next_load_delay_old_value = 0;
+}
+
+void Core::FlushPipeline()
+{
+  // loads are flushed
+  FlushLoadDelay();
 
   // not in a branch delay slot
   m_branched = false;
@@ -214,7 +219,7 @@ void Core::WriteRegDelayed(Reg rd, u32 value)
 
   // save the old value, this will be returned if the register is read in the next instruction
   m_next_load_delay_reg = rd;
-  m_next_load_delay_old_value = m_regs.r[static_cast<u8>(rd)];
+  m_next_load_delay_old_value = ReadReg(rd);
   m_regs.r[static_cast<u8>(rd)] = value;
 }
 
diff --git a/src/pse/cpu_core.h b/src/pse/cpu_core.h
index c358e4717..6634492b9 100644
--- a/src/pse/cpu_core.h
+++ b/src/pse/cpu_core.h
@@ -71,6 +71,9 @@ private:
   void Branch(u32 target);
   void RaiseException(Exception excode);
 
+  // flushes any load delays if present
+  void FlushLoadDelay();
+
   // clears pipeline of load/branch delays
   void FlushPipeline();