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Common/CPUDetect: Use consistant naming for ARM targets
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302b08023e
commit
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@ -8,6 +8,8 @@
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#define CPU_X86 1
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#define CPU_X86 1
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#elif defined(_M_ARM64)
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#elif defined(_M_ARM64)
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#define CPU_AARCH64 1
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#define CPU_AARCH64 1
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#elif defined(_M_ARM)
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#define CPU_AARCH32 1
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#else
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#else
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#error Unknown architecture.
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#error Unknown architecture.
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#endif
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#endif
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@ -21,7 +23,7 @@
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#elif defined(__aarch64__)
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#elif defined(__aarch64__)
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#define CPU_AARCH64 1
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#define CPU_AARCH64 1
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#elif defined(__arm__)
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#elif defined(__arm__)
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#define CPU_ARM 1
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#define CPU_AARCH32 1
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#else
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#else
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#error Unknown architecture.
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#error Unknown architecture.
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#endif
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#endif
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@ -148,7 +148,7 @@ void JitCodeBuffer::CommitCode(u32 length)
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if (length == 0)
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if (length == 0)
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return;
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return;
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#if defined(CPU_ARM) || defined(CPU_AARCH64)
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#if defined(CPU_AARCH32) || defined(CPU_AARCH64)
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// ARM instruction and data caches are not coherent, we need to flush after every block.
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// ARM instruction and data caches are not coherent, we need to flush after every block.
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FlushInstructionCache(m_free_code_ptr, length);
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FlushInstructionCache(m_free_code_ptr, length);
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#endif
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#endif
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@ -163,7 +163,7 @@ void JitCodeBuffer::CommitFarCode(u32 length)
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if (length == 0)
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if (length == 0)
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return;
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return;
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#if defined(CPU_ARM) || defined(CPU_AARCH64)
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#if defined(CPU_AARCH32) || defined(CPU_AARCH64)
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// ARM instruction and data caches are not coherent, we need to flush after every block.
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// ARM instruction and data caches are not coherent, we need to flush after every block.
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FlushInstructionCache(m_free_far_code_ptr, length);
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FlushInstructionCache(m_free_far_code_ptr, length);
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#endif
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#endif
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