Common/CPUDetect: Use consistant naming for ARM targets

This commit is contained in:
Connor McLaughlin 2020-11-21 01:52:39 +10:00
parent 302b08023e
commit dba42cf323
2 changed files with 5 additions and 3 deletions

View file

@ -8,6 +8,8 @@
#define CPU_X86 1 #define CPU_X86 1
#elif defined(_M_ARM64) #elif defined(_M_ARM64)
#define CPU_AARCH64 1 #define CPU_AARCH64 1
#elif defined(_M_ARM)
#define CPU_AARCH32 1
#else #else
#error Unknown architecture. #error Unknown architecture.
#endif #endif
@ -21,7 +23,7 @@
#elif defined(__aarch64__) #elif defined(__aarch64__)
#define CPU_AARCH64 1 #define CPU_AARCH64 1
#elif defined(__arm__) #elif defined(__arm__)
#define CPU_ARM 1 #define CPU_AARCH32 1
#else #else
#error Unknown architecture. #error Unknown architecture.
#endif #endif

View file

@ -148,7 +148,7 @@ void JitCodeBuffer::CommitCode(u32 length)
if (length == 0) if (length == 0)
return; return;
#if defined(CPU_ARM) || defined(CPU_AARCH64) #if defined(CPU_AARCH32) || defined(CPU_AARCH64)
// ARM instruction and data caches are not coherent, we need to flush after every block. // ARM instruction and data caches are not coherent, we need to flush after every block.
FlushInstructionCache(m_free_code_ptr, length); FlushInstructionCache(m_free_code_ptr, length);
#endif #endif
@ -163,7 +163,7 @@ void JitCodeBuffer::CommitFarCode(u32 length)
if (length == 0) if (length == 0)
return; return;
#if defined(CPU_ARM) || defined(CPU_AARCH64) #if defined(CPU_AARCH32) || defined(CPU_AARCH64)
// ARM instruction and data caches are not coherent, we need to flush after every block. // ARM instruction and data caches are not coherent, we need to flush after every block.
FlushInstructionCache(m_free_far_code_ptr, length); FlushInstructionCache(m_free_far_code_ptr, length);
#endif #endif