From ddf52cc8c73baa3f47030bd52ada322993e62741 Mon Sep 17 00:00:00 2001 From: Connor McLaughlin Date: Sat, 4 Apr 2020 00:11:43 +1000 Subject: [PATCH] GPU/SW: Implement interlaced display --- src/core/gpu_sw.cpp | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/src/core/gpu_sw.cpp b/src/core/gpu_sw.cpp index 909b8af70..8829dab9f 100644 --- a/src/core/gpu_sw.cpp +++ b/src/core/gpu_sw.cpp @@ -94,15 +94,34 @@ void GPU_SW::UpdateDisplay() m_host_display->ClearDisplayTexture(); return; } - else if (m_GPUSTAT.display_area_color_depth_24) + else if (IsInterlacedDisplayEnabled()) { - CopyOut24Bit(m_vram.data() + vram_offset_y * VRAM_WIDTH + vram_offset_x, VRAM_WIDTH, - m_display_texture_buffer.data(), display_width, display_width, display_height); + const u32 field = GetInterlacedField(); + if (m_GPUSTAT.display_area_color_depth_24) + { + CopyOut24Bit(m_vram.data() + (vram_offset_y + field) * VRAM_WIDTH + vram_offset_x, VRAM_WIDTH * 2, + m_display_texture_buffer.data() + field * display_width, display_width * 2, display_width, + display_height / 2); + } + else + { + CopyOut15Bit(m_vram.data() + (vram_offset_y + field) * VRAM_WIDTH + vram_offset_x, VRAM_WIDTH * 2, + m_display_texture_buffer.data() + field * display_width, display_width * 2, display_width, + display_height / 2); + } } else { - CopyOut15Bit(m_vram.data() + vram_offset_y * VRAM_WIDTH + vram_offset_x, VRAM_WIDTH, - m_display_texture_buffer.data(), display_width, display_width, display_height); + if (m_GPUSTAT.display_area_color_depth_24) + { + CopyOut24Bit(m_vram.data() + vram_offset_y * VRAM_WIDTH + vram_offset_x, VRAM_WIDTH, + m_display_texture_buffer.data(), display_width, display_width, display_height); + } + else + { + CopyOut15Bit(m_vram.data() + vram_offset_y * VRAM_WIDTH + vram_offset_x, VRAM_WIDTH, + m_display_texture_buffer.data(), display_width, display_width, display_height); + } } m_host_display->UpdateTexture(m_display_texture.get(), 0, 0, display_width, display_height,