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https://github.com/RetroDECK/Duckstation.git
synced 2024-11-30 01:25:51 +00:00
Bus: Further tweaks to access timing
Matches closely to my console now. Fixes Otona No Asobi again.
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7d66569d69
commit
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@ -25,7 +25,7 @@ Log_SetChannel(Bus);
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#define FIXUP_HALFWORD_WRITE_VALUE(offset, value) ((value) << (((offset)&u32(1)) * 8u))
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// Offset and value remapping for (w32) registers from nocash docs.
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void FixupUnalignedWordAccessW32(u32& offset, u32& value)
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ALWAYS_INLINE static void FixupUnalignedWordAccessW32(u32& offset, u32& value)
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{
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const u32 byte_offset = offset & u32(3);
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offset &= ~u32(3);
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@ -426,39 +426,79 @@ void Bus::DoWriteSIO(MemoryAccessSize size, u32 offset, u32 value)
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u32 Bus::DoReadCDROM(MemoryAccessSize size, u32 offset)
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{
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// TODO: Splitting of half/word reads.
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Assert(size == MemoryAccessSize::Byte);
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return ZeroExtend32(m_cdrom->ReadRegister(offset));
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switch (size)
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{
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case MemoryAccessSize::Word:
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{
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const u32 b0 = ZeroExtend32(m_cdrom->ReadRegister(offset));
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const u32 b1 = ZeroExtend32(m_cdrom->ReadRegister(offset + 1u));
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const u32 b2 = ZeroExtend32(m_cdrom->ReadRegister(offset + 2u));
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const u32 b3 = ZeroExtend32(m_cdrom->ReadRegister(offset + 3u));
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return b0 | (b1 << 8) | (b2 << 16) | (b3 << 24);
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}
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case MemoryAccessSize::HalfWord:
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{
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const u32 lsb = ZeroExtend32(m_cdrom->ReadRegister(offset));
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const u32 msb = ZeroExtend32(m_cdrom->ReadRegister(offset + 1u));
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return lsb | (msb << 8);
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}
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case MemoryAccessSize::Byte:
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default:
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return ZeroExtend32(m_cdrom->ReadRegister(offset));
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}
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}
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void Bus::DoWriteCDROM(MemoryAccessSize size, u32 offset, u32 value)
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{
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// TODO: Splitting of half/word reads.
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Assert(size == MemoryAccessSize::Byte);
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m_cdrom->WriteRegister(offset, Truncate8(value));
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switch (size)
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{
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case MemoryAccessSize::Word:
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{
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m_cdrom->WriteRegister(offset, Truncate8(value & 0xFFu));
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m_cdrom->WriteRegister(offset + 1u, Truncate8((value >> 8) & 0xFFu));
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m_cdrom->WriteRegister(offset + 2u, Truncate8((value >> 16) & 0xFFu));
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m_cdrom->WriteRegister(offset + 3u, Truncate8((value >> 24) & 0xFFu));
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}
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break;
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case MemoryAccessSize::HalfWord:
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{
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m_cdrom->WriteRegister(offset, Truncate8(value & 0xFFu));
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m_cdrom->WriteRegister(offset + 1u, Truncate8((value >> 8) & 0xFFu));
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}
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break;
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case MemoryAccessSize::Byte:
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default:
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return m_cdrom->WriteRegister(offset, Truncate8(value));
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}
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}
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u32 Bus::DoReadGPU(MemoryAccessSize size, u32 offset)
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{
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Assert(size == MemoryAccessSize::Word);
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return m_gpu->ReadRegister(offset);
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u32 value = m_gpu->ReadRegister(offset);
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FixupUnalignedWordAccessW32(offset, value);
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return value;
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}
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void Bus::DoWriteGPU(MemoryAccessSize size, u32 offset, u32 value)
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{
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Assert(size == MemoryAccessSize::Word);
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FixupUnalignedWordAccessW32(offset, value);
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m_gpu->WriteRegister(offset, value);
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}
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u32 Bus::DoReadMDEC(MemoryAccessSize size, u32 offset)
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{
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Assert(size == MemoryAccessSize::Word);
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return m_mdec->ReadRegister(offset);
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u32 value = m_mdec->ReadRegister(offset);
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FixupUnalignedWordAccessW32(offset, value);
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return value;
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}
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void Bus::DoWriteMDEC(MemoryAccessSize size, u32 offset, u32 value)
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{
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Assert(size == MemoryAccessSize::Word);
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FixupUnalignedWordAccessW32(offset, value);
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m_mdec->WriteRegister(offset, value);
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}
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@ -44,7 +44,7 @@ TickCount Bus::DoRAMAccess(u32 offset, u32& value)
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}
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}
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return (type == MemoryAccessType::Read) ? 3 : 0;
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return (type == MemoryAccessType::Read) ? 4 : 0;
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}
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template<MemoryAccessType type, MemoryAccessSize size>
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@ -110,7 +110,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadMemoryControl(size, address & PAD_MASK);
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return 1;
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return 2;
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}
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else
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{
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@ -123,7 +123,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadPad(size, address & PAD_MASK);
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return 1;
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return 2;
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}
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else
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{
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@ -136,7 +136,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadSIO(size, address & SIO_MASK);
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return 1;
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return 2;
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}
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else
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{
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@ -149,7 +149,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadMemoryControl2(size, address & PAD_MASK);
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return 1;
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return 2;
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}
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else
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{
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@ -162,7 +162,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadInterruptController(size, address & INTERRUPT_CONTROLLER_MASK);
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return 1;
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return 2;
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}
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else
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{
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@ -175,7 +175,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadDMA(size, address & DMA_MASK);
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return 1;
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return 2;
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}
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else
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{
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@ -188,7 +188,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadTimers(size, address & TIMERS_MASK);
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return 1;
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return 2;
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}
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else
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{
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@ -218,7 +218,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadGPU(size, address & GPU_MASK);
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return 1;
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return 2;
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}
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else
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{
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@ -231,7 +231,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
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if constexpr (type == MemoryAccessType::Read)
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{
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value = DoReadMDEC(size, address & MDEC_MASK);
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return 1;
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return 2;
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}
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else
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{
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