From f071497be5f09d3e85b7b88a820347a671c160aa Mon Sep 17 00:00:00 2001 From: Connor McLaughlin Date: Sun, 4 Oct 2020 00:11:03 +1000 Subject: [PATCH] CPU/Recompiler: Optimize beq zero, zero, addr to unconditional branch Seems to exist in some BIOS code. Credit to @Dillonb for the idea. --- src/core/cpu_recompiler_code_generator.cpp | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/src/core/cpu_recompiler_code_generator.cpp b/src/core/cpu_recompiler_code_generator.cpp index f350844a3..c46b08c30 100644 --- a/src/core/cpu_recompiler_code_generator.cpp +++ b/src/core/cpu_recompiler_code_generator.cpp @@ -1736,11 +1736,20 @@ bool CodeGenerator::Compile_Branch(const CodeBlockInstruction& cbi) // npc = pc + (sext(imm) << 2) Value branch_target = CalculatePC(cbi.instruction.i.imm_sext32() << 2); - // branch <- rs op rt - Value lhs = m_register_cache.ReadGuestRegister(cbi.instruction.i.rs, true, true); - Value rhs = m_register_cache.ReadGuestRegister(cbi.instruction.i.rt); - const Condition condition = (cbi.instruction.op == InstructionOp::beq) ? Condition::Equal : Condition::NotEqual; - DoBranch(condition, lhs, rhs, Reg::count, std::move(branch_target)); + // beq zero, zero, addr -> unconditional branch + if (cbi.instruction.op == InstructionOp::beq && cbi.instruction.i.rs == Reg::zero && + cbi.instruction.i.rt == Reg::zero) + { + DoBranch(Condition::Always, Value(), Value(), Reg::count, std::move(branch_target)); + } + else + { + // branch <- rs op rt + Value lhs = m_register_cache.ReadGuestRegister(cbi.instruction.i.rs, true, true); + Value rhs = m_register_cache.ReadGuestRegister(cbi.instruction.i.rt); + const Condition condition = (cbi.instruction.op == InstructionOp::beq) ? Condition::Equal : Condition::NotEqual; + DoBranch(condition, lhs, rhs, Reg::count, std::move(branch_target)); + } } break;