Xargon/Duckstation
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6055 commits 1 branch 1 tag 100 MiB
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71 commits

Author SHA1 Message Date
Stenzek 33f5d9cb9c System: Remove BIOS from save state 
Makes the states smaller, as well as not creating potential piracy
issues when sending across the wire.
 2023-03-16 19:34:01 +10:00
Stenzek 1fcf16fc81 System: Store BIOS image info/hash after loading 2023-03-16 19:22:54 +10:00
Connor McLaughlin 3e16746e85 Pad: Convert to namespace 2023-01-11 19:15:59 +10:00
Connor McLaughlin 835834f8f4 SIO: Convert to namespace 2023-01-11 19:15:59 +10:00
Connor McLaughlin 0683b9fa0e InterruptController: Convert to namespace 2023-01-11 19:15:59 +10:00
Connor McLaughlin db364d0e95 Timers: Convert to namespace 2023-01-11 19:15:59 +10:00
Connor McLaughlin 3acf569d67 DMA: Convert to namespace 2023-01-11 19:15:59 +10:00
Connor McLaughlin dd73811628 CDROM: Convert to namespace 2023-01-09 22:20:27 +10:00
Connor McLaughlin 1c8ef86f12 MDEC: Convert to namespace 2022-12-20 21:18:30 +10:00
Connor McLaughlin 8c7a192128 Misc: Add copyright/license statement to applicable files 
Should've did this in the beginning.
 2022-12-04 21:03:49 +10:00
Connor McLaughlin 5b2c18e27c SPU: Convert to namespace 2022-08-15 17:22:23 +10:00
Silent c98e0bd096
Bus: Added RAM, RAM_SIZE and RAM_MASK exports for external debugger usage 
Useful e.g. for Cheat Engine.
 2022-07-31 10:43:26 +02:00
Connor McLaughlin b42b5501f6 UI: Massive revamp, new features and improvements 2022-07-22 21:19:54 +10:00
Connor McLaughlin b7fbde31a7 Move utility classes from common to own static lib 2022-07-21 17:29:58 +10:00
Silent 270899dbdb
Make DoSafeMemoryAccess return true properly for RAM, BIOS, dcache writes 
Fixes broken cheats when writing to unaligned addresses,
maybe also achievements.
 2021-09-24 10:07:04 +02:00
Connor McLaughlin f7f121f036 Bus: Handle unaligned accesses in safe memory routines 2021-09-15 12:24:33 +10:00
Connor McLaughlin 8dcd68b0a8 CPU: Make Safe{Read,Write}Memory{Byte,Halfword,Word} truely safe 2021-09-10 15:53:14 +10:00
Connor McLaughlin 1ed1d641a6 CPU/Recompiler: Don't use intepreter icache when falling back 
Fixes broken rendering in TOCA 2.

It has self-modifying code every frame, which gets falled back to the
interpreter, and using the interpreter's icache, which resulted in
stale code executing.
 2021-05-20 12:19:23 +10:00
Connor McLaughlin 729675f497 Bus: Fix memory reserving when 8MB RAM is enabled 2021-05-08 20:36:34 +10:00
Connor McLaughlin e382df0d41 Support expanding RAM to 8MB (dev console) 2021-05-03 12:43:33 +10:00
Connor McLaughlin 40731b49fc Bus: Handle CPU-internal narrow writes 
The full 32-bits of the GPR are used.

Fixes SoundScope in the BIOS Shell.
 2021-04-26 22:08:18 +10:00
Connor McLaughlin 3106c797d9 CPU: Reduce severity of some log statements 2021-04-19 15:19:08 +10:00
Connor McLaughlin 6868ad4326 Bus: Don't reserve entire fastmem region on Android 2021-04-17 16:33:25 +10:00
Connor McLaughlin 58f5c99100 Bus: Fix incorrect EPC for IBE exceptions 2021-04-14 19:01:43 +10:00
Connor McLaughlin e087e6f3a2 CPU/Recompiler: Prevent using fastmem when cache is isolated 
No point even trying since it's just going to fault.
 2021-04-12 02:08:56 +10:00
Connor McLaughlin 922d320523 CPU/Recompiler: Reserve whole fastmem region to avoid clashes 2021-04-11 12:42:51 +10:00
Connor McLaughlin 701edb335a Various warning fixes 2021-02-06 19:19:55 +10:00
C.W. Betts 662d6e9711 Fix possible log formatting errors. 2021-02-04 17:54:51 -07:00
Connor McLaughlin f832dca975 Bus: Don't force inline EXP1/EXP2 access 2021-01-06 01:02:30 +10:00
Connor McLaughlin f3cdfe97a7 Bus/EXP2: Support openbios putc address 2021-01-06 00:56:35 +10:00
Connor McLaughlin e3262fc0a4 CPU: Compile fix for debug builds 2021-01-05 00:46:41 +10:00
Connor McLaughlin 68dc052432 Bus: Don't leak shared memory when starting->stopping->starting 2020-12-27 00:50:08 +10:00
Connor McLaughlin 9fd1d606d7 Bus: Add memory region access helpers 2020-12-17 11:57:46 +10:00
Connor McLaughlin 9089c97339 CPU: Drop cache control log to dev level 2020-12-04 01:19:00 +10:00
Connor McLaughlin bf2e38aed5 CPU/Recompiler: Implement LUT-based fastmem 2020-11-24 14:49:21 +10:00
Connor McLaughlin 028a5c60d7 Bus: Fix failed safe instruction reads raising guest exceptions 2020-11-21 18:39:03 +10:00
Connor McLaughlin a03bca2f72 CPU: Make fastmem a compile-time feature (support 32-bit targets) 2020-11-21 18:39:03 +10:00
Albert Liu c698519d44 Bus: Log writes to additional POST registers 2020-11-09 09:02:00 -08:00
Albert Liu f3522b7b70 Bus: Stub out EXP3 and unknown EXP accesses 2020-11-09 09:02:00 -08:00
Connor McLaughlin be63d893cd CPU: Use partial icache fills for non-line-aligned addresses 2020-10-30 00:44:40 +10:00
Connor McLaughlin 3b3ad0c1cb Bus: Fix icache fills from BIOS failing 2020-10-30 00:44:39 +10:00
Connor McLaughlin f14270fc4b Bus: Ignore reads to nocash EXP2 area 2020-10-30 00:44:39 +10:00
Connor McLaughlin 392c7af738 Bus: Fix assertion failing if booting fails 2020-10-28 17:31:25 +10:00
Connor McLaughlin 7f795d25aa CPU/Recompiler: Don't try fastmem for RAM mirrors 2020-10-26 22:07:52 +10:00
Connor McLaughlin 6a4a4c62d7 CPU/Recompiler: Use fastmem instead of global for RAM loads 2020-10-19 02:23:04 +10:00
Connor McLaughlin b704c37e91 CPU/Recompiler: Implement speculative constants 2020-10-18 14:54:38 +10:00
Connor McLaughlin 7566c45f64 CPU/Recompiler: Implement fastmem 2020-10-18 14:54:38 +10:00
Connor McLaughlin 0afdc04d88 CPU/Recompiler: Optimize constant reads (and some writes) 2020-10-18 14:54:38 +10:00
Connor McLaughlin 19d6037b99 CPU: Implement instruction cache simulation 
Implemented for all execution modes. Disabled by default in the cached
interpreter and recompiler, always enabled in the pure interpreter.
 2020-08-29 22:07:40 +10:00
Connor McLaughlin 1d5f810a4b CPU/Recompiler: Disable memory access exceptions by default 
This means it'll no longer pass amidog's CPU test in the default config.
But no games rely on this. You can enable it in advanced options if you
want to pass the CPU test.
 2020-08-08 23:44:13 +10:00