mirror of
https://github.com/RetroDECK/Duckstation.git
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120 lines
3.3 KiB
C++
120 lines
3.3 KiB
C++
// SPDX-FileCopyrightText: 2019-2024 Connor McLaughlin <stenzek@gmail.com>
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// SPDX-License-Identifier: (GPL-3.0 OR CC-BY-NC-ND-4.0)
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#include "interrupt_controller.h"
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#include "cpu_core.h"
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#include "util/state_wrapper.h"
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#include "common/log.h"
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Log_SetChannel(InterruptController);
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namespace InterruptController {
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static constexpr u32 REGISTER_WRITE_MASK = (u32(1) << NUM_IRQS) - 1;
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static constexpr u32 DEFAULT_INTERRUPT_MASK = 0;
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static void UpdateCPUInterruptRequest();
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static u32 s_interrupt_status_register = 0;
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static u32 s_interrupt_mask_register = DEFAULT_INTERRUPT_MASK;
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static u32 s_interrupt_line_state = 0;
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[[maybe_unused]] static constexpr std::array<const char*, static_cast<size_t>(IRQ::MaxCount)> s_irq_names = {
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{"VBLANK", "GPU", "CDROM", "DMA", "TMR0", "TMR1", "TMR2", "PAD", "SIO", "SPU", "IRQ10"}};
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} // namespace InterruptController
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void InterruptController::Reset()
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{
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s_interrupt_status_register = 0;
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s_interrupt_mask_register = DEFAULT_INTERRUPT_MASK;
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s_interrupt_line_state = 0;
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}
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bool InterruptController::DoState(StateWrapper& sw)
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{
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sw.Do(&s_interrupt_status_register);
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sw.Do(&s_interrupt_mask_register);
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sw.DoEx(&s_interrupt_line_state, 63, s_interrupt_status_register);
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return !sw.HasError();
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}
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void InterruptController::SetLineState(IRQ irq, bool state)
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{
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// Interupts are edge-triggered, so only set the flag in the status register on a 0-1 transition.
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const u32 bit = (1u << static_cast<u32>(irq));
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const u32 prev_state = s_interrupt_line_state;
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s_interrupt_line_state = (s_interrupt_line_state & ~bit) | (state ? bit : 0u);
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if (s_interrupt_line_state == prev_state)
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return;
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#ifdef _DEBUG
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if (!(prev_state & bit) && state)
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DEBUG_LOG("{} IRQ triggered", s_irq_names[static_cast<size_t>(irq)]);
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else if ((prev_state & bit) && !state)
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DEBUG_LOG("{} IRQ line inactive", s_irq_names[static_cast<size_t>(irq)]);
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#endif
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s_interrupt_status_register |= (state ? (prev_state ^ s_interrupt_line_state) : 0u) & s_interrupt_line_state;
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UpdateCPUInterruptRequest();
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}
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u32 InterruptController::ReadRegister(u32 offset)
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{
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switch (offset)
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{
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case 0x00: // I_STATUS
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return s_interrupt_status_register;
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case 0x04: // I_MASK
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return s_interrupt_mask_register;
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[[unlikely]] default:
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ERROR_LOG("Invalid read at offset 0x{:08X}", offset);
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return UINT32_C(0xFFFFFFFF);
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}
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}
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void InterruptController::WriteRegister(u32 offset, u32 value)
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{
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switch (offset)
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{
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case 0x00: // I_STATUS
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{
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#ifdef _DEBUG
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const u32 cleared_bits = (s_interrupt_status_register & ~value);
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for (u32 i = 0; i < static_cast<u32>(IRQ::MaxCount); i++)
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{
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if (cleared_bits & (1u << i))
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DEBUG_LOG("{} IRQ cleared", s_irq_names[i]);
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}
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#endif
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s_interrupt_status_register = s_interrupt_status_register & (value & REGISTER_WRITE_MASK);
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UpdateCPUInterruptRequest();
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}
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break;
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case 0x04: // I_MASK
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{
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DEBUG_LOG("Interrupt mask <- 0x{:08X}", value);
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s_interrupt_mask_register = value & REGISTER_WRITE_MASK;
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UpdateCPUInterruptRequest();
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}
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break;
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default:
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[[unlikely]] ERROR_LOG("Invalid write at offset 0x{:08X}", offset);
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break;
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}
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}
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ALWAYS_INLINE_RELEASE void InterruptController::UpdateCPUInterruptRequest()
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{
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const bool state = (s_interrupt_status_register & s_interrupt_mask_register) != 0;
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CPU::SetIRQRequest(state);
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}
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