mirror of
https://github.com/RetroDECK/Duckstation.git
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b6f871d2b9
* CPU/Recompiler: Use rel32 call where possible for no-args * JitCodeBuffer: Support using preallocated buffer * CPU/Recompiler/AArch64: Use bl instead of blr for short branches * CPU/CodeCache: Allocate recompiler buffer in program space This means we don't need 64-bit moves for every call out of the recompiler. * GTE: Don't store as u16 and load as u32 * CPU/Recompiler: Add methods to emit global load/stores * GTE: Convert class to namespace * CPU/Recompiler: Call GTE functions directly * Settings: Turn into a global variable * GPU: Replace local pointers with global * InterruptController: Turn into a global pointer * System: Replace local pointers with global * Timers: Turn into a global instance * DMA: Turn into a global instance * SPU: Turn into a global instance * CDROM: Turn into a global instance * MDEC: Turn into a global instance * Pad: Turn into a global instance * SIO: Turn into a global instance * CDROM: Move audio FIFO to the heap * CPU/Recompiler: Drop ASMFunctions No longer needed since we have code in the same 4GB window. * CPUCodeCache: Turn class into namespace * Bus: Local pointer -> global pointers * CPU: Turn class into namespace * Bus: Turn into namespace * GTE: Store registers in CPU state struct Allows relative addressing on ARM. * CPU/Recompiler: Align code storage to page size * CPU/Recompiler: Fix relative branches on A64 * HostInterface: Local references to global * System: Turn into a namespace, move events out * Add guard pages * Android: Fix build
93 lines
2.1 KiB
C++
93 lines
2.1 KiB
C++
#include "interrupt_controller.h"
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#include "common/log.h"
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#include "common/state_wrapper.h"
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#include "cpu_core.h"
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Log_SetChannel(InterruptController);
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InterruptController g_interrupt_controller;
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InterruptController::InterruptController() = default;
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InterruptController::~InterruptController() = default;
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void InterruptController::Initialize()
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{
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Reset();
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}
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void InterruptController::Shutdown() {}
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void InterruptController::Reset()
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{
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m_interrupt_status_register = 0;
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m_interrupt_mask_register = DEFAULT_INTERRUPT_MASK;
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}
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bool InterruptController::DoState(StateWrapper& sw)
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{
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sw.Do(&m_interrupt_status_register);
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sw.Do(&m_interrupt_mask_register);
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return !sw.HasError();
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}
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void InterruptController::InterruptRequest(IRQ irq)
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{
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const u32 bit = (u32(1) << static_cast<u32>(irq));
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m_interrupt_status_register |= bit;
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UpdateCPUInterruptRequest();
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}
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u32 InterruptController::ReadRegister(u32 offset)
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{
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switch (offset)
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{
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case 0x00: // I_STATUS
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return m_interrupt_status_register;
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case 0x04: // I_MASK
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return m_interrupt_mask_register;
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default:
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Log_ErrorPrintf("Invalid read at offset 0x%08X", offset);
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return UINT32_C(0xFFFFFFFF);
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}
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}
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void InterruptController::WriteRegister(u32 offset, u32 value)
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{
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switch (offset)
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{
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case 0x00: // I_STATUS
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{
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if ((m_interrupt_status_register & ~value) != 0)
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Log_DebugPrintf("Clearing bits 0x%08X", (m_interrupt_status_register & ~value));
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m_interrupt_status_register = m_interrupt_status_register & (value & REGISTER_WRITE_MASK);
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UpdateCPUInterruptRequest();
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}
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break;
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case 0x04: // I_MASK
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{
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Log_DebugPrintf("Interrupt mask <- 0x%08X", value);
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m_interrupt_mask_register = value & REGISTER_WRITE_MASK;
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UpdateCPUInterruptRequest();
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}
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break;
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default:
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Log_ErrorPrintf("Invalid write at offset 0x%08X", offset);
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break;
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}
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}
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void InterruptController::UpdateCPUInterruptRequest()
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{
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// external interrupts set bit 10 only?
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if ((m_interrupt_status_register & m_interrupt_mask_register) != 0)
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CPU::SetExternalInterrupt(2);
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else
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CPU::ClearExternalInterrupt(2);
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}
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