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108 lines
3.2 KiB
C++
108 lines
3.2 KiB
C++
// SPDX-FileCopyrightText: 2016 iCatButler, 2019-2023 Connor McLaughlin <stenzek@gmail.com>
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// SPDX-License-Identifier: GPL-2.0+
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#pragma once
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#include "cpu_core.h"
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namespace CPU::PGXP {
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void Initialize();
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void Reset();
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void Shutdown();
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// -- GTE functions
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// Transforms
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void GTE_PushSXYZ2f(float x, float y, float z, u32 v);
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int GTE_NCLIP_valid(u32 sxy0, u32 sxy1, u32 sxy2);
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float GTE_NCLIP();
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// Data transfer tracking
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void CPU_MFC2(u32 instr, u32 rdVal); // copy GTE data reg to GPR reg (MFC2)
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void CPU_MTC2(u32 instr, u32 rtVal); // copy GPR reg to GTE data reg (MTC2)
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// Memory Access
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void CPU_LWC2(u32 instr, u32 addr, u32 rtVal); // copy memory to GTE reg
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void CPU_SWC2(u32 instr, u32 addr, u32 rtVal); // copy GTE reg to memory
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bool GetPreciseVertex(u32 addr, u32 value, int x, int y, int xOffs, int yOffs, float* out_x, float* out_y,
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float* out_w);
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// -- CPU functions
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void CPU_LW(u32 instr, u32 addr, u32 rtVal);
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void CPU_LH(u32 instr, u32 addr, u32 rtVal);
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void CPU_LHU(u32 instr, u32 addr, u32 rtVal);
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void CPU_LBx(u32 instr, u32 addr, u32 rtVal);
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void CPU_SB(u32 instr, u32 addr, u32 rtVal);
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void CPU_SH(u32 instr, u32 addr, u32 rtVal);
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void CPU_SW(u32 instr, u32 addr, u32 rtVal);
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void CPU_MOVE(u32 Rd, u32 Rs, u32 rsVal);
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ALWAYS_INLINE static u32 PackMoveArgs(Reg rd, Reg rs)
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{
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return (static_cast<u32>(rd) << 8) | static_cast<u32>(rs);
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}
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void CPU_MOVE_Packed(u32 rd_and_rs, u32 rsVal);
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// Arithmetic with immediate value
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void CPU_ADDI(u32 instr, u32 rsVal);
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void CPU_ANDI(u32 instr, u32 rsVal);
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void CPU_ORI(u32 instr, u32 rsVal);
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void CPU_XORI(u32 instr, u32 rsVal);
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void CPU_SLTI(u32 instr, u32 rsVal);
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void CPU_SLTIU(u32 instr, u32 rsVal);
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// Load Upper
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void CPU_LUI(u32 instr);
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// Register Arithmetic
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void CPU_ADD(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_SUB(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_AND_(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_OR_(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_XOR_(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_NOR(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_SLT(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_SLTU(u32 instr, u32 rsVal, u32 rtVal);
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// Register mult/div
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void CPU_MULT(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_MULTU(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_DIV(u32 instr, u32 rsVal, u32 rtVal);
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void CPU_DIVU(u32 instr, u32 rsVal, u32 rtVal);
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// Shift operations (sa)
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void CPU_SLL(u32 instr, u32 rtVal);
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void CPU_SRL(u32 instr, u32 rtVal);
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void CPU_SRA(u32 instr, u32 rtVal);
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// Shift operations variable
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void CPU_SLLV(u32 instr, u32 rtVal, u32 rsVal);
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void CPU_SRLV(u32 instr, u32 rtVal, u32 rsVal);
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void CPU_SRAV(u32 instr, u32 rtVal, u32 rsVal);
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// CP0 Data transfer tracking
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void CPU_MFC0(u32 instr, u32 rdVal);
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void CPU_MTC0(u32 instr, u32 rdVal, u32 rtVal);
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ALWAYS_INLINE void TryMove(Reg rd, Reg rs, Reg rt)
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{
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u32 src;
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if (rs == Reg::zero)
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src = static_cast<u32>(rt);
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else if (rt == Reg::zero)
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src = static_cast<u32>(rs);
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else
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return;
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CPU_MOVE(static_cast<u32>(rd), src, g_state.regs.r[src]);
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}
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ALWAYS_INLINE void TryMoveImm(Reg rd, Reg rs, u32 imm)
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{
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if (imm == 0)
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{
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const u32 src = static_cast<u32>(rs);
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CPU_MOVE(static_cast<u32>(rd), src, g_state.regs.r[src]);
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}
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}
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} // namespace CPU::PGXP
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