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https://github.com/RetroDECK/Duckstation.git
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150 lines
5.2 KiB
C++
150 lines
5.2 KiB
C++
#ifndef _C4_CPU_HPP_
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#define _C4_CPU_HPP_
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/** @file cpu.hpp Provides processor information macros
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* @ingroup basic_headers */
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// see also https://sourceforge.net/p/predef/wiki/Architectures/
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// see also https://sourceforge.net/p/predef/wiki/Endianness/
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// see also https://github.com/googlesamples/android-ndk/blob/android-mk/hello-jni/jni/hello-jni.c
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// see http://code.qt.io/cgit/qt/qtbase.git/tree/src/corelib/global/qprocessordetection.h
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#ifdef __ORDER_LITTLE_ENDIAN__
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# define _C4EL __ORDER_LITTLE_ENDIAN__
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#else
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# define _C4EL 1234
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#endif
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#ifdef __ORDER_BIG_ENDIAN__
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# define _C4EB __ORDER_BIG_ENDIAN__
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#else
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# define _C4EB 4321
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#endif
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// mixed byte order (eg, PowerPC or ia64)
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#define _C4EM 1111
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#if defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(_M_X64)
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# define C4_CPU_X86_64
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# define C4_WORDSIZE 8
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# define C4_BYTE_ORDER _C4EL
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#elif defined(__i386) || defined(__i386__) || defined(_M_IX86)
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# define C4_CPU_X86
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# define C4_WORDSIZE 4
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# define C4_BYTE_ORDER _C4EL
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#elif defined(__arm__) || defined(_M_ARM) \
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|| defined(__TARGET_ARCH_ARM) || defined(__aarch64__) || defined(_M_ARM64)
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# if defined(__aarch64__) || defined(_M_ARM64)
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# define C4_CPU_ARM64
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# define C4_CPU_ARMV8
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# define C4_WORDSIZE 8
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# else
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# define C4_CPU_ARM
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# define C4_WORDSIZE 4
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# if defined(__ARM_ARCH_8__) || defined(__ARM_ARCH_8A__) \
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|| (defined(__ARCH_ARM) && __ARCH_ARM >= 8) \
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|| (defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM >= 8)
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# define C4_CPU_ARMV8
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# elif defined(__ARM_ARCH_7__) || defined(_ARM_ARCH_7) \
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|| defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) \
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|| defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) \
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|| defined(__ARM_ARCH_7EM__) \
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|| (defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM >= 7) \
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|| (defined(_M_ARM) && _M_ARM >= 7)
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# define C4_CPU_ARMV7
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# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
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|| defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) \
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|| defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) \
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|| defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6KZ__) \
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|| (defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM >= 6)
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# define C4_CPU_ARMV6
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# elif defined(__ARM_ARCH_5TEJ__) \
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|| defined(__ARM_ARCH_5TE__) \
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|| (defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM >= 5)
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# define C4_CPU_ARMV5
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# elif defined(__ARM_ARCH_4T__) \
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|| (defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM >= 4)
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# define C4_CPU_ARMV4
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# else
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# error "unknown CPU architecture: ARM"
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# endif
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# endif
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# if defined(__ARMEL__) || defined(__LITTLE_ENDIAN__) || defined(__AARCH64EL__) \
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|| (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)) \
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|| defined(_MSC_VER) // winarm64 does not provide any of the above macros,
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// but advises little-endianess:
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// https://docs.microsoft.com/en-us/cpp/build/overview-of-arm-abi-conventions?view=msvc-170
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// So if it is visual studio compiling, we'll assume little endian.
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# define C4_BYTE_ORDER _C4EL
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# elif defined(__ARMEB__) || defined(__BIG_ENDIAN__) || defined(__AARCH64EB__) \
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|| (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__))
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# define C4_BYTE_ORDER _C4EB
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# elif defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_PDP_ENDIAN__)
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# define C4_BYTE_ORDER _C4EM
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# else
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# error "unknown endianness"
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# endif
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#elif defined(__ia64) || defined(__ia64__) || defined(_M_IA64)
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# define C4_CPU_IA64
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# define C4_WORDSIZE 8
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# define C4_BYTE_ORDER _C4EM
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// itanium is bi-endian - check byte order below
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#elif defined(__ppc__) || defined(__ppc) || defined(__powerpc__) \
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|| defined(_ARCH_COM) || defined(_ARCH_PWR) || defined(_ARCH_PPC) \
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|| defined(_M_MPPC) || defined(_M_PPC)
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# if defined(__ppc64__) || defined(__powerpc64__) || defined(__64BIT__)
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# define C4_CPU_PPC64
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# define C4_WORDSIZE 8
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# else
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# define C4_CPU_PPC
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# define C4_WORDSIZE 4
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# endif
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# define C4_BYTE_ORDER _C4EM
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// ppc is bi-endian - check byte order below
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#elif defined(__s390x__) || defined(__zarch__) || defined(__SYSC_ZARCH_)
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# define C4_CPU_S390_X
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# define C4_WORDSIZE 8
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# define C4_BYTE_ORDER _C4EB
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#elif defined(__xtensa__) || defined(__XTENSA__)
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# define C4_CPU_XTENSA
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# define C4_WORDSIZE 4
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// not sure about this...
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# if defined(__XTENSA_EL__) || defined(__xtensa_el__)
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# define C4_BYTE_ORDER _C4EL
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# else
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# define C4_BYTE_ORDER _C4EB
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# endif
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#elif defined(__riscv)
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# if __riscv_xlen == 64
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# define C4_CPU_RISCV64
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# define C4_WORDSIZE 8
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# else
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# define C4_CPU_RISCV32
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# define C4_WORDSIZE 4
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# endif
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# define C4_BYTE_ORDER _C4EL
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#elif defined(__EMSCRIPTEN__)
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# define C4_BYTE_ORDER _C4EL
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# define C4_WORDSIZE 4
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#elif defined(SWIG)
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# error "please define CPU architecture macros when compiling with swig"
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#else
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# error "unknown CPU architecture"
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#endif
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#define C4_LITTLE_ENDIAN (C4_BYTE_ORDER == _C4EL)
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#define C4_BIG_ENDIAN (C4_BYTE_ORDER == _C4EB)
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#define C4_MIXED_ENDIAN (C4_BYTE_ORDER == _C4EM)
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#endif /* _C4_CPU_HPP_ */
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