mirror of
https://github.com/RetroDECK/Duckstation.git
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182 lines
5 KiB
C++
182 lines
5 KiB
C++
#pragma once
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#include "common/bitfield.h"
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#include "util/memory_arena.h"
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#include "types.h"
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#include <array>
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#include <bitset>
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#include <optional>
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#include <string>
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#include <vector>
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class StateWrapper;
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namespace Bus {
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enum : u32
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{
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RAM_BASE = 0x00000000,
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RAM_2MB_SIZE = 0x200000,
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RAM_2MB_MASK = RAM_2MB_SIZE - 1,
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RAM_8MB_SIZE = 0x800000,
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RAM_8MB_MASK = RAM_8MB_SIZE - 1,
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RAM_MIRROR_END = 0x800000,
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EXP1_BASE = 0x1F000000,
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EXP1_SIZE = 0x800000,
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EXP1_MASK = EXP1_SIZE - 1,
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MEMCTRL_BASE = 0x1F801000,
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MEMCTRL_SIZE = 0x40,
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MEMCTRL_MASK = MEMCTRL_SIZE - 1,
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PAD_BASE = 0x1F801040,
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PAD_SIZE = 0x10,
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PAD_MASK = PAD_SIZE - 1,
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SIO_BASE = 0x1F801050,
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SIO_SIZE = 0x10,
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SIO_MASK = SIO_SIZE - 1,
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MEMCTRL2_BASE = 0x1F801060,
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MEMCTRL2_SIZE = 0x10,
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MEMCTRL2_MASK = MEMCTRL2_SIZE - 1,
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INTERRUPT_CONTROLLER_BASE = 0x1F801070,
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INTERRUPT_CONTROLLER_SIZE = 0x10,
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INTERRUPT_CONTROLLER_MASK = INTERRUPT_CONTROLLER_SIZE - 1,
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DMA_BASE = 0x1F801080,
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DMA_SIZE = 0x80,
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DMA_MASK = DMA_SIZE - 1,
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TIMERS_BASE = 0x1F801100,
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TIMERS_SIZE = 0x40,
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TIMERS_MASK = TIMERS_SIZE - 1,
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CDROM_BASE = 0x1F801800,
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CDROM_SIZE = 0x10,
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CDROM_MASK = CDROM_SIZE - 1,
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GPU_BASE = 0x1F801810,
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GPU_SIZE = 0x10,
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GPU_MASK = GPU_SIZE - 1,
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MDEC_BASE = 0x1F801820,
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MDEC_SIZE = 0x10,
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MDEC_MASK = MDEC_SIZE - 1,
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SPU_BASE = 0x1F801C00,
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SPU_SIZE = 0x400,
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SPU_MASK = 0x3FF,
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EXP2_BASE = 0x1F802000,
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EXP2_SIZE = 0x2000,
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EXP2_MASK = EXP2_SIZE - 1,
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EXP3_BASE = 0x1FA00000,
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EXP3_SIZE = 0x1,
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EXP3_MASK = EXP3_SIZE - 1,
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BIOS_BASE = 0x1FC00000,
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BIOS_SIZE = 0x80000,
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BIOS_MASK = 0x7FFFF,
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};
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enum : u32
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{
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MEMCTRL_REG_COUNT = 9
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};
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enum : TickCount
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{
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RAM_READ_TICKS = 6
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};
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enum : size_t
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{
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// Our memory arena contains storage for RAM.
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MEMORY_ARENA_SIZE = RAM_8MB_SIZE,
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// Offsets within the memory arena.
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MEMORY_ARENA_RAM_OFFSET = 0,
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#ifdef WITH_MMAP_FASTMEM
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// Fastmem region size is 4GB to cover the entire 32-bit address space.
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FASTMEM_REGION_SIZE = UINT64_C(0x100000000),
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#endif
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};
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enum : u32
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{
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RAM_2MB_CODE_PAGE_COUNT = (RAM_2MB_SIZE + (HOST_PAGE_SIZE + 1)) / HOST_PAGE_SIZE,
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RAM_8MB_CODE_PAGE_COUNT = (RAM_8MB_SIZE + (HOST_PAGE_SIZE + 1)) / HOST_PAGE_SIZE,
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FASTMEM_LUT_NUM_PAGES = 0x100000, // 0x100000000 >> 12
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FASTMEM_LUT_NUM_SLOTS = FASTMEM_LUT_NUM_PAGES * 2,
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};
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bool Initialize();
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void Shutdown();
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void Reset();
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bool DoState(StateWrapper& sw);
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CPUFastmemMode GetFastmemMode();
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u8* GetFastmemBase();
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void UpdateFastmemViews(CPUFastmemMode mode);
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bool CanUseFastmemForAddress(VirtualMemoryAddress address);
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void SetExpansionROM(std::vector<u8> data);
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void SetBIOS(const std::vector<u8>& image);
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extern std::bitset<RAM_8MB_CODE_PAGE_COUNT> m_ram_code_bits;
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extern u8* g_ram; // 2MB-8MB RAM
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extern u32 g_ram_size; // Active size of RAM.
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extern u32 g_ram_mask; // Active address bits for RAM.
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extern u8 g_bios[BIOS_SIZE]; // 512K BIOS ROM
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/// Returns true if the address specified is writable (RAM).
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ALWAYS_INLINE static bool IsRAMAddress(PhysicalMemoryAddress address)
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{
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return address < RAM_MIRROR_END;
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}
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/// Returns the code page index for a RAM address.
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ALWAYS_INLINE static u32 GetRAMCodePageIndex(PhysicalMemoryAddress address)
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{
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return (address & g_ram_mask) / HOST_PAGE_SIZE;
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}
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/// Returns true if the specified page contains code.
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bool IsRAMCodePage(u32 index);
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/// Flags a RAM region as code, so we know when to invalidate blocks.
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void SetRAMCodePage(u32 index);
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/// Unflags a RAM region as code, the code cache will no longer be notified when writes occur.
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void ClearRAMCodePage(u32 index);
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/// Clears all code bits for RAM regions.
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void ClearRAMCodePageFlags();
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/// Returns true if the specified address is in a code page.
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bool IsCodePageAddress(PhysicalMemoryAddress address);
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/// Returns true if the range specified overlaps with a code page.
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bool HasCodePagesInRange(PhysicalMemoryAddress start_address, u32 size);
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/// Returns the number of cycles stolen by DMA RAM access.
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ALWAYS_INLINE TickCount GetDMARAMTickCount(u32 word_count)
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{
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// DMA is using DRAM Hyper Page mode, allowing it to access DRAM rows at 1 clock cycle per word (effectively around
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// 17 clks per 16 words, due to required row address loading, probably plus some further minimal overload due to
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// refresh cycles). This is making DMA much faster than CPU memory accesses (CPU DRAM access takes 1 opcode cycle
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// plus 6 waitstates, ie. 7 cycles in total).
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return static_cast<TickCount>(word_count + ((word_count + 15) / 16));
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}
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enum class MemoryRegion
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{
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RAM,
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RAMMirror1,
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RAMMirror2,
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RAMMirror3,
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EXP1,
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Scratchpad,
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BIOS,
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Count
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};
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std::optional<MemoryRegion> GetMemoryRegionForAddress(PhysicalMemoryAddress address);
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PhysicalMemoryAddress GetMemoryRegionStart(MemoryRegion region);
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PhysicalMemoryAddress GetMemoryRegionEnd(MemoryRegion region);
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u8* GetMemoryRegionPointer(MemoryRegion region);
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std::optional<PhysicalMemoryAddress> SearchMemory(PhysicalMemoryAddress start_address, const u8* pattern,
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const u8* mask, u32 pattern_length);
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} // namespace Bus
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