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https://github.com/RetroDECK/Duckstation.git
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19d6037b99
Implemented for all execution modes. Disabled by default in the cached interpreter and recompiler, always enabled in the pure interpreter.
76 lines
2.7 KiB
C++
76 lines
2.7 KiB
C++
#pragma once
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#include "cpu_core.h"
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namespace CPU {
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// exceptions
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void RaiseException(Exception excode);
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void RaiseException(u32 CAUSE_bits, u32 EPC);
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ALWAYS_INLINE static bool HasPendingInterrupt()
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{
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// const bool do_interrupt = g_state.m_cop0_regs.sr.IEc && ((g_state.m_cop0_regs.cause.Ip & g_state.m_cop0_regs.sr.Im)
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// != 0);
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const bool do_interrupt = g_state.cop0_regs.sr.IEc &&
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(((g_state.cop0_regs.cause.bits & g_state.cop0_regs.sr.bits) & (UINT32_C(0xFF) << 8)) != 0);
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const bool interrupt_delay = g_state.interrupt_delay;
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g_state.interrupt_delay = false;
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return do_interrupt && !interrupt_delay;
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}
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ALWAYS_INLINE static void DispatchInterrupt()
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{
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// If the instruction we're about to execute is a GTE instruction, delay dispatching the interrupt until the next
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// instruction. For some reason, if we don't do this, we end up with incorrectly sorted polygons and flickering..
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if (g_state.next_instruction.IsCop2Instruction())
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return;
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// Interrupt raising occurs before the start of the instruction.
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RaiseException(
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Cop0Registers::CAUSE::MakeValueForException(Exception::INT, g_state.next_instruction_is_branch_delay_slot,
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g_state.branch_was_taken, g_state.next_instruction.cop.cop_n),
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g_state.regs.pc);
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}
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// icache stuff
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ALWAYS_INLINE bool IsCachedAddress(VirtualMemoryAddress address)
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{
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// KUSEG, KSEG0
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return (address >> 29) <= 4;
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}
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ALWAYS_INLINE u32 GetICacheLine(VirtualMemoryAddress address)
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{
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return ((address >> 4) & 0xFFu);
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}
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ALWAYS_INLINE u32 GetICacheLineOffset(VirtualMemoryAddress address)
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{
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return (address & (ICACHE_LINE_SIZE - 1));
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}
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ALWAYS_INLINE u32 GetICacheTagForAddress(VirtualMemoryAddress address)
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{
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return (address & ICACHE_TAG_ADDRESS_MASK);
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}
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ALWAYS_INLINE bool CompareICacheTag(VirtualMemoryAddress address)
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{
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const u32 line = GetICacheLine(address);
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return (g_state.icache_tags[line] == GetICacheTagForAddress(address));
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}
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TickCount GetInstructionReadTicks(VirtualMemoryAddress address);
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TickCount GetICacheFillTicks(VirtualMemoryAddress address);
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u32 FillICache(VirtualMemoryAddress address);
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void CheckAndUpdateICacheTags(u32 line_count, TickCount uncached_ticks);
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// defined in cpu_memory.cpp - memory access functions which return false if an exception was thrown.
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bool FetchInstruction();
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bool SafeReadInstruction(VirtualMemoryAddress addr, u32* value);
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bool ReadMemoryByte(VirtualMemoryAddress addr, u8* value);
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bool ReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value);
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bool ReadMemoryWord(VirtualMemoryAddress addr, u32* value);
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bool WriteMemoryByte(VirtualMemoryAddress addr, u8 value);
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bool WriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value);
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bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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} // namespace CPU
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