mirror of
https://github.com/RetroDECK/Duckstation.git
synced 2024-10-23 15:45:42 +00:00
553 lines
15 KiB
C++
553 lines
15 KiB
C++
#include "dma.h"
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#include "bus.h"
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#include "cdrom.h"
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#include "common/log.h"
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#include "common/state_wrapper.h"
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#include "common/string_util.h"
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#include "cpu_core.h"
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#include "gpu.h"
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#include "interrupt_controller.h"
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#include "mdec.h"
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#include "spu.h"
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#include "system.h"
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Log_SetChannel(DMA);
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DMA g_dma;
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DMA::DMA() = default;
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DMA::~DMA() = default;
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void DMA::Initialize()
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{
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m_max_slice_ticks = g_settings.dma_max_slice_ticks;
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m_halt_ticks = g_settings.dma_halt_ticks;
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m_transfer_buffer.resize(32);
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m_unhalt_event = TimingEvents::CreateTimingEvent("DMA Transfer Unhalt", 1, m_max_slice_ticks,
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std::bind(&DMA::UnhaltTransfer, this, std::placeholders::_1), false);
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Reset();
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}
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void DMA::Shutdown()
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{
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m_unhalt_event.reset();
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}
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void DMA::Reset()
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{
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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ChannelState& cs = m_state[i];
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cs.base_address = 0;
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cs.block_control.bits = 0;
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cs.channel_control.bits = 0;
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cs.request = false;
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}
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m_DPCR.bits = 0x07654321;
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m_DICR.bits = 0;
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m_halt_ticks_remaining = 0;
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m_unhalt_event->Deactivate();
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}
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bool DMA::DoState(StateWrapper& sw)
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{
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sw.Do(&m_halt_ticks_remaining);
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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ChannelState& cs = m_state[i];
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sw.Do(&cs.base_address);
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sw.Do(&cs.block_control.bits);
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sw.Do(&cs.channel_control.bits);
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sw.Do(&cs.request);
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}
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sw.Do(&m_DPCR.bits);
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sw.Do(&m_DICR.bits);
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if (sw.IsReading())
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{
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if (m_halt_ticks_remaining > 0)
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m_unhalt_event->SetIntervalAndSchedule(m_halt_ticks_remaining);
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else
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m_unhalt_event->Deactivate();
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}
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return !sw.HasError();
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}
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u32 DMA::ReadRegister(u32 offset)
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{
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const u32 channel_index = offset >> 4;
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if (channel_index < 7)
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{
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switch (offset & UINT32_C(0x0F))
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{
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case 0x00:
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{
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Log_TracePrintf("DMA%u base address -> 0x%08X", channel_index, m_state[channel_index].base_address);
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return m_state[channel_index].base_address;
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}
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case 0x04:
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{
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Log_TracePrintf("DMA%u block control -> 0x%08X", channel_index, m_state[channel_index].block_control.bits);
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return m_state[channel_index].block_control.bits;
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}
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case 0x08:
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{
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Log_TracePrintf("DMA%u channel control -> 0x%08X", channel_index, m_state[channel_index].channel_control.bits);
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return m_state[channel_index].channel_control.bits;
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}
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default:
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break;
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}
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}
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else
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{
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if (offset == 0x70)
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{
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Log_TracePrintf("DPCR -> 0x%08X", m_DPCR.bits);
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return m_DPCR.bits;
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}
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else if (offset == 0x74)
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{
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Log_TracePrintf("DPCR -> 0x%08X", m_DPCR.bits);
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return m_DICR.bits;
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}
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}
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Log_ErrorPrintf("Unhandled register read: %02X", offset);
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return UINT32_C(0xFFFFFFFF);
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}
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void DMA::WriteRegister(u32 offset, u32 value)
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{
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const u32 channel_index = offset >> 4;
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if (channel_index < 7)
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{
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ChannelState& state = m_state[channel_index];
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switch (offset & UINT32_C(0x0F))
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{
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case 0x00:
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{
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state.base_address = value & BASE_ADDRESS_MASK;
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Log_TracePrintf("DMA channel %u base address <- 0x%08X", channel_index, state.base_address);
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return;
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}
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case 0x04:
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{
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Log_TracePrintf("DMA channel %u block control <- 0x%08X", channel_index, value);
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state.block_control.bits = value;
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return;
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}
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case 0x08:
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{
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state.channel_control.bits = (state.channel_control.bits & ~ChannelState::ChannelControl::WRITE_MASK) |
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(value & ChannelState::ChannelControl::WRITE_MASK);
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Log_TracePrintf("DMA channel %u channel control <- 0x%08X", channel_index, state.channel_control.bits);
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// start/trigger bit must be enabled for OTC
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if (static_cast<Channel>(channel_index) == Channel::OTC)
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SetRequest(static_cast<Channel>(channel_index), state.channel_control.start_trigger);
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if (CanTransferChannel(static_cast<Channel>(channel_index)))
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TransferChannel(static_cast<Channel>(channel_index));
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return;
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}
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default:
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break;
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}
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}
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else
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{
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switch (offset)
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{
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case 0x70:
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{
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Log_TracePrintf("DPCR <- 0x%08X", value);
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m_DPCR.bits = value;
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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if (CanTransferChannel(static_cast<Channel>(i)))
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{
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if (!TransferChannel(static_cast<Channel>(i)))
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break;
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}
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}
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return;
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}
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case 0x74:
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{
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Log_TracePrintf("DCIR <- 0x%08X", value);
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m_DICR.bits = (m_DICR.bits & ~DICR_WRITE_MASK) | (value & DICR_WRITE_MASK);
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m_DICR.bits = m_DICR.bits & ~(value & DICR_RESET_MASK);
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m_DICR.UpdateMasterFlag();
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return;
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}
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default:
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break;
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}
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}
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Log_ErrorPrintf("Unhandled register write: %02X <- %08X", offset, value);
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}
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void DMA::SetRequest(Channel channel, bool request)
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{
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ChannelState& cs = m_state[static_cast<u32>(channel)];
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if (cs.request == request)
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return;
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cs.request = request;
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if (CanTransferChannel(channel))
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TransferChannel(channel);
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}
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bool DMA::CanTransferChannel(Channel channel) const
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{
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if (!m_DPCR.GetMasterEnable(channel))
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return false;
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const ChannelState& cs = m_state[static_cast<u32>(channel)];
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if (!cs.channel_control.enable_busy)
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return false;
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if (cs.channel_control.sync_mode != SyncMode::Manual && IsTransferHalted())
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return false;
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return cs.request;
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}
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bool DMA::IsTransferHalted() const
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{
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return m_unhalt_event->IsActive();
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}
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void DMA::UpdateIRQ()
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{
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m_DICR.UpdateMasterFlag();
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if (m_DICR.master_flag)
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{
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Log_TracePrintf("Firing DMA master interrupt");
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g_interrupt_controller.InterruptRequest(InterruptController::IRQ::DMA);
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}
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}
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bool DMA::TransferChannel(Channel channel)
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{
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ChannelState& cs = m_state[static_cast<u32>(channel)];
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const bool copy_to_device = cs.channel_control.copy_to_device;
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// start/trigger bit is cleared on beginning of transfer
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cs.channel_control.start_trigger = false;
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PhysicalMemoryAddress current_address = cs.base_address;
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const PhysicalMemoryAddress increment = cs.channel_control.address_step_reverse ? static_cast<u32>(-4) : UINT32_C(4);
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switch (cs.channel_control.sync_mode)
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{
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case SyncMode::Manual:
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{
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const u32 word_count = cs.block_control.manual.GetWordCount();
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Log_DebugPrintf("DMA%u: Copying %u words %s 0x%08X", static_cast<u32>(channel), word_count,
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copy_to_device ? "from" : "to", current_address & ADDRESS_MASK);
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TickCount used_ticks;
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if (copy_to_device)
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used_ticks = TransferMemoryToDevice(channel, current_address & ADDRESS_MASK, increment, word_count);
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else
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used_ticks = TransferDeviceToMemory(channel, current_address & ADDRESS_MASK, increment, word_count);
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CPU::AddPendingTicks(used_ticks);
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}
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break;
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case SyncMode::LinkedList:
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{
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TickCount used_ticks = 0;
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if (!copy_to_device)
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{
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Panic("Linked list not implemented for DMA reads");
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return true;
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}
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Log_DebugPrintf("DMA%u: Copying linked list starting at 0x%08X to device", static_cast<u32>(channel),
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current_address & ADDRESS_MASK);
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u8* ram_pointer = Bus::g_ram;
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bool halt_transfer = false;
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while (cs.request)
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{
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u32 header;
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std::memcpy(&header, &ram_pointer[current_address & ADDRESS_MASK], sizeof(header));
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used_ticks++;
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const u32 word_count = header >> 24;
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const u32 next_address = header & UINT32_C(0x00FFFFFF);
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Log_TracePrintf(" .. linked list entry at 0x%08X size=%u(%u words) next=0x%08X", current_address & ADDRESS_MASK,
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word_count * UINT32_C(4), word_count, next_address);
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if (word_count > 0)
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{
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used_ticks +=
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TransferMemoryToDevice(channel, (current_address + sizeof(header)) & ADDRESS_MASK, 4, word_count);
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}
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else if ((current_address & ADDRESS_MASK) == (next_address & ADDRESS_MASK))
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{
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current_address = next_address;
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halt_transfer = true;
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break;
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}
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current_address = next_address;
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if (current_address & UINT32_C(0x800000))
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break;
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if (used_ticks >= m_max_slice_ticks)
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{
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halt_transfer = true;
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break;
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}
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}
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cs.base_address = current_address;
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CPU::AddPendingTicks(used_ticks);
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if (current_address & UINT32_C(0x800000))
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break;
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if (halt_transfer)
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{
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// stall the transfer for a bit if we ran for too long
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HaltTransfer(m_halt_ticks);
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return false;
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}
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else
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{
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// linked list not yet complete
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return true;
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}
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}
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break;
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case SyncMode::Request:
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{
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Log_DebugPrintf("DMA%u: Copying %u blocks of size %u (%u total words) %s 0x%08X", static_cast<u32>(channel),
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cs.block_control.request.GetBlockCount(), cs.block_control.request.GetBlockSize(),
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cs.block_control.request.GetBlockCount() * cs.block_control.request.GetBlockSize(),
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copy_to_device ? "from" : "to", current_address & ADDRESS_MASK);
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const u32 block_size = cs.block_control.request.GetBlockSize();
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u32 blocks_remaining = cs.block_control.request.GetBlockCount();
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TickCount used_ticks = 0;
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if (copy_to_device)
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{
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do
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{
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blocks_remaining--;
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used_ticks += TransferMemoryToDevice(channel, current_address & ADDRESS_MASK, increment, block_size);
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current_address = (current_address + (increment * block_size));
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} while (cs.request && blocks_remaining > 0);
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}
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else
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{
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do
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{
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blocks_remaining--;
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used_ticks += TransferDeviceToMemory(channel, current_address & ADDRESS_MASK, increment, block_size);
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current_address = (current_address + (increment * block_size));
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} while (cs.request && blocks_remaining > 0);
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}
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cs.base_address = current_address & BASE_ADDRESS_MASK;
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cs.block_control.request.block_count = blocks_remaining;
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CPU::AddPendingTicks(used_ticks);
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// finish transfer later if the request was cleared
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if (blocks_remaining > 0)
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return true;
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}
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break;
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default:
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Panic("Unimplemented sync mode");
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break;
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}
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// start/busy bit is cleared on end of transfer
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cs.channel_control.enable_busy = false;
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if (m_DICR.IsIRQEnabled(channel))
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{
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Log_DebugPrintf("Set DMA interrupt for channel %u", static_cast<u32>(channel));
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m_DICR.SetIRQFlag(channel);
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UpdateIRQ();
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}
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return true;
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}
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void DMA::HaltTransfer(TickCount duration)
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{
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m_halt_ticks_remaining += duration;
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Log_DebugPrintf("Halting DMA for %d ticks", m_halt_ticks_remaining);
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DebugAssert(!m_unhalt_event->IsActive());
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m_unhalt_event->SetIntervalAndSchedule(m_halt_ticks_remaining);
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}
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void DMA::UnhaltTransfer(TickCount ticks)
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{
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Log_DebugPrintf("Resuming DMA after %d ticks, %d ticks late", ticks, -(m_halt_ticks_remaining - ticks));
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m_halt_ticks_remaining -= ticks;
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m_unhalt_event->Deactivate();
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// TODO: Use channel priority. But doing it in ascending order is probably good enough.
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// Main thing is that OTC happens after GPU, because otherwise it'll wipe out the LL.
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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if (CanTransferChannel(static_cast<Channel>(i)))
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{
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if (!TransferChannel(static_cast<Channel>(i)))
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return;
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}
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}
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// We didn't run too long, so reset timer.
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m_halt_ticks_remaining = 0;
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}
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TickCount DMA::TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u32 word_count)
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{
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const u32* src_pointer = reinterpret_cast<u32*>(Bus::g_ram + address);
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if (channel != Channel::GPU &&
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(static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & ADDRESS_MASK) <= address))
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{
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// Use temp buffer if it's wrapping around
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if (m_transfer_buffer.size() < word_count)
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m_transfer_buffer.resize(word_count);
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src_pointer = m_transfer_buffer.data();
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u8* ram_pointer = Bus::g_ram;
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for (u32 i = 0; i < word_count; i++)
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{
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std::memcpy(&m_transfer_buffer[i], &ram_pointer[address], sizeof(u32));
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address = (address + increment) & ADDRESS_MASK;
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}
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}
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switch (channel)
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{
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case Channel::GPU:
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{
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if (g_gpu->BeginDMAWrite())
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{
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u8* ram_pointer = Bus::g_ram;
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for (u32 i = 0; i < word_count; i++)
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{
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u32 value;
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std::memcpy(&value, &ram_pointer[address], sizeof(u32));
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g_gpu->DMAWrite(address, value);
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address = (address + increment) & ADDRESS_MASK;
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}
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g_gpu->EndDMAWrite();
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}
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}
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break;
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case Channel::SPU:
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g_spu.DMAWrite(src_pointer, word_count);
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break;
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case Channel::MDECin:
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g_mdec.DMAWrite(src_pointer, word_count);
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break;
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case Channel::CDROM:
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case Channel::MDECout:
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case Channel::PIO:
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default:
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Panic("Unhandled DMA channel for device write");
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break;
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}
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return Bus::GetDMARAMTickCount(word_count);
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}
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TickCount DMA::TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u32 word_count)
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{
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if (channel == Channel::OTC)
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{
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// clear ordering table
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u8* ram_pointer = Bus::g_ram;
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const u32 word_count_less_1 = word_count - 1;
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for (u32 i = 0; i < word_count_less_1; i++)
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{
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u32 value = ((address - 4) & ADDRESS_MASK);
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std::memcpy(&ram_pointer[address], &value, sizeof(value));
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address = (address - 4) & ADDRESS_MASK;
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}
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const u32 terminator = UINT32_C(0xFFFFFF);
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std::memcpy(&ram_pointer[address], &terminator, sizeof(terminator));
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Bus::InvalidateCodePages(address, word_count);
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return Bus::GetDMARAMTickCount(word_count);
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}
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u32* dest_pointer = reinterpret_cast<u32*>(&Bus::g_ram[address]);
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if (static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & ADDRESS_MASK) <= address)
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{
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// Use temp buffer if it's wrapping around
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if (m_transfer_buffer.size() < word_count)
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m_transfer_buffer.resize(word_count);
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dest_pointer = m_transfer_buffer.data();
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}
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// Read from device.
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switch (channel)
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{
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case Channel::GPU:
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g_gpu->DMARead(dest_pointer, word_count);
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break;
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case Channel::CDROM:
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g_cdrom.DMARead(dest_pointer, word_count);
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break;
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case Channel::SPU:
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g_spu.DMARead(dest_pointer, word_count);
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break;
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case Channel::MDECout:
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g_mdec.DMARead(dest_pointer, word_count);
|
|
break;
|
|
|
|
default:
|
|
Panic("Unhandled DMA channel for device read");
|
|
std::fill_n(dest_pointer, word_count, UINT32_C(0xFFFFFFFF));
|
|
break;
|
|
}
|
|
|
|
if (dest_pointer == m_transfer_buffer.data())
|
|
{
|
|
u8* ram_pointer = Bus::g_ram;
|
|
for (u32 i = 0; i < word_count; i++)
|
|
{
|
|
std::memcpy(&ram_pointer[address], &m_transfer_buffer[i], sizeof(u32));
|
|
address = (address + increment) & ADDRESS_MASK;
|
|
}
|
|
}
|
|
|
|
Bus::InvalidateCodePages(address, word_count);
|
|
return Bus::GetDMARAMTickCount(word_count);
|
|
}
|