mirror of
https://github.com/RetroDECK/Duckstation.git
synced 2024-10-23 23:55:42 +00:00
296 lines
9.2 KiB
C++
296 lines
9.2 KiB
C++
#pragma once
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#include "common/bitfield.h"
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#include "types.h"
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#include <array>
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#include <bitset>
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#include <string>
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#include <vector>
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class StateWrapper;
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namespace CPU {
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class Core;
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class CodeCache;
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} // namespace CPU
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class DMA;
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class InterruptController;
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class GPU;
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class CDROM;
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class Pad;
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class Timers;
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class SPU;
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class MDEC;
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class SIO;
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class System;
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class Bus
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{
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friend DMA;
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public:
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Bus();
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~Bus();
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void Initialize(CPU::Core* cpu, CPU::CodeCache* cpu_code_cache, DMA* dma, InterruptController* interrupt_controller,
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GPU* gpu, CDROM* cdrom, Pad* pad, Timers* timers, SPU* spu, MDEC* mdec, SIO* sio);
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void Reset();
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bool DoState(StateWrapper& sw);
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bool ReadByte(PhysicalMemoryAddress address, u8* value);
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bool ReadHalfWord(PhysicalMemoryAddress address, u16* value);
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bool ReadWord(PhysicalMemoryAddress address, u32* value);
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bool WriteByte(PhysicalMemoryAddress address, u8 value);
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bool WriteHalfWord(PhysicalMemoryAddress address, u16 value);
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bool WriteWord(PhysicalMemoryAddress address, u32 value);
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template<MemoryAccessType type, MemoryAccessSize size>
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TickCount DispatchAccess(PhysicalMemoryAddress address, u32& value);
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// Optimized variant for burst/multi-word read/writing.
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TickCount ReadWords(PhysicalMemoryAddress address, u32* words, u32 word_count);
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TickCount WriteWords(PhysicalMemoryAddress address, const u32* words, u32 word_count);
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void SetExpansionROM(std::vector<u8> data);
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void SetBIOS(const std::vector<u8>& image);
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// changing interfaces
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void SetGPU(GPU* gpu) { m_gpu = gpu; }
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/// Returns the address which should be used for code caching (i.e. removes mirrors).
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ALWAYS_INLINE static PhysicalMemoryAddress UnmirrorAddress(PhysicalMemoryAddress address)
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{
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// RAM
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if (address < 0x800000)
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return address & UINT32_C(0x1FFFFF);
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else
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return address;
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}
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/// Returns true if the address specified is cacheable (RAM or BIOS).
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ALWAYS_INLINE static bool IsCacheableAddress(PhysicalMemoryAddress address)
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{
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return (address < RAM_MIRROR_END) || (address >= BIOS_BASE && address < (BIOS_BASE + BIOS_SIZE));
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}
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/// Returns true if the address specified is writable (RAM).
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ALWAYS_INLINE static bool IsRAMAddress(PhysicalMemoryAddress address) { return address < RAM_MIRROR_END; }
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/// Flags a RAM region as code, so we know when to invalidate blocks.
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ALWAYS_INLINE void SetRAMCodePage(u32 index) { m_ram_code_bits[index] = true; }
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/// Unflags a RAM region as code, the code cache will no longer be notified when writes occur.
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ALWAYS_INLINE void ClearRAMCodePage(u32 index) { m_ram_code_bits[index] = false; }
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/// Clears all code bits for RAM regions.
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ALWAYS_INLINE void ClearRAMCodePageFlags() { m_ram_code_bits.reset(); }
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private:
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enum : u32
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{
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RAM_BASE = 0x00000000,
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RAM_SIZE = 0x200000,
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RAM_MASK = RAM_SIZE - 1,
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RAM_MIRROR_END = 0x800000,
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EXP1_BASE = 0x1F000000,
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EXP1_SIZE = 0x800000,
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EXP1_MASK = EXP1_SIZE - 1,
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MEMCTRL_BASE = 0x1F801000,
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MEMCTRL_SIZE = 0x40,
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MEMCTRL_MASK = MEMCTRL_SIZE - 1,
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PAD_BASE = 0x1F801040,
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PAD_SIZE = 0x10,
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PAD_MASK = PAD_SIZE - 1,
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SIO_BASE = 0x1F801050,
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SIO_SIZE = 0x10,
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SIO_MASK = SIO_SIZE - 1,
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MEMCTRL2_BASE = 0x1F801060,
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MEMCTRL2_SIZE = 0x10,
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MEMCTRL2_MASK = MEMCTRL_SIZE - 1,
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INTERRUPT_CONTROLLER_BASE = 0x1F801070,
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INTERRUPT_CONTROLLER_SIZE = 0x10,
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INTERRUPT_CONTROLLER_MASK = INTERRUPT_CONTROLLER_SIZE - 1,
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DMA_BASE = 0x1F801080,
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DMA_SIZE = 0x80,
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DMA_MASK = DMA_SIZE - 1,
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TIMERS_BASE = 0x1F801100,
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TIMERS_SIZE = 0x40,
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TIMERS_MASK = TIMERS_SIZE - 1,
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CDROM_BASE = 0x1F801800,
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CDROM_SIZE = 0x10,
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CDROM_MASK = CDROM_SIZE - 1,
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GPU_BASE = 0x1F801810,
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GPU_SIZE = 0x10,
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GPU_MASK = GPU_SIZE - 1,
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MDEC_BASE = 0x1F801820,
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MDEC_SIZE = 0x10,
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MDEC_MASK = MDEC_SIZE - 1,
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SPU_BASE = 0x1F801C00,
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SPU_SIZE = 0x400,
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SPU_MASK = 0x3FF,
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EXP2_BASE = 0x1F802000,
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EXP2_SIZE = 0x2000,
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EXP2_MASK = EXP2_SIZE - 1,
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BIOS_BASE = 0x1FC00000,
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BIOS_SIZE = 0x80000
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};
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enum : u32
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{
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MEMCTRL_REG_COUNT = 9
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};
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union MEMDELAY
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{
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u32 bits;
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BitField<u32, u8, 4, 4> access_time; // cycles
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BitField<u32, bool, 8, 1> use_com0_time;
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BitField<u32, bool, 9, 1> use_com1_time;
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BitField<u32, bool, 10, 1> use_com2_time;
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BitField<u32, bool, 11, 1> use_com3_time;
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BitField<u32, bool, 12, 1> data_bus_16bit;
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BitField<u32, u8, 16, 5> memory_window_size;
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static constexpr u32 WRITE_MASK = 0b10101111'00011111'11111111'11111111;
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};
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union COMDELAY
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{
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u32 bits;
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BitField<u32, u8, 0, 4> com0;
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BitField<u32, u8, 4, 4> com1;
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BitField<u32, u8, 8, 4> com2;
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BitField<u32, u8, 12, 4> com3;
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BitField<u32, u8, 16, 2> comunk;
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static constexpr u32 WRITE_MASK = 0b00000000'00000011'11111111'11111111;
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};
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union MEMCTRL
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{
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u32 regs[MEMCTRL_REG_COUNT];
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struct
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{
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u32 exp1_base;
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u32 exp2_base;
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MEMDELAY exp1_delay_size;
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MEMDELAY exp3_delay_size;
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MEMDELAY bios_delay_size;
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MEMDELAY spu_delay_size;
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MEMDELAY cdrom_delay_size;
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MEMDELAY exp2_delay_size;
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COMDELAY common_delay;
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};
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};
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static std::tuple<TickCount, TickCount, TickCount> CalculateMemoryTiming(MEMDELAY mem_delay, COMDELAY common_delay);
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void RecalculateMemoryTimings();
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template<MemoryAccessType type, MemoryAccessSize size>
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TickCount DoRAMAccess(u32 offset, u32& value);
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template<MemoryAccessType type, MemoryAccessSize size>
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TickCount DoBIOSAccess(u32 offset, u32& value);
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TickCount DoInvalidAccess(MemoryAccessType type, MemoryAccessSize size, PhysicalMemoryAddress address, u32& value);
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u32 DoReadEXP1(MemoryAccessSize size, u32 offset);
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void DoWriteEXP1(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadEXP2(MemoryAccessSize size, u32 offset);
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void DoWriteEXP2(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadMemoryControl(MemoryAccessSize size, u32 offset);
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void DoWriteMemoryControl(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadMemoryControl2(MemoryAccessSize size, u32 offset);
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void DoWriteMemoryControl2(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadPad(MemoryAccessSize size, u32 offset);
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void DoWritePad(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadSIO(MemoryAccessSize size, u32 offset);
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void DoWriteSIO(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadCDROM(MemoryAccessSize size, u32 offset);
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void DoWriteCDROM(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadGPU(MemoryAccessSize size, u32 offset);
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void DoWriteGPU(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadMDEC(MemoryAccessSize size, u32 offset);
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void DoWriteMDEC(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadInterruptController(MemoryAccessSize size, u32 offset);
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void DoWriteInterruptController(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadDMA(MemoryAccessSize size, u32 offset);
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void DoWriteDMA(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadTimers(MemoryAccessSize size, u32 offset);
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void DoWriteTimers(MemoryAccessSize size, u32 offset, u32 value);
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u32 DoReadSPU(MemoryAccessSize size, u32 offset);
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void DoWriteSPU(MemoryAccessSize size, u32 offset, u32 value);
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void DoInvalidateCodeCache(u32 page_index);
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/// Direct access to RAM - used by DMA.
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ALWAYS_INLINE u8* GetRAM() { return m_ram.data(); }
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/// Returns the number of cycles stolen by DMA RAM access.
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ALWAYS_INLINE static TickCount GetDMARAMTickCount(u32 word_count)
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{
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// DMA is using DRAM Hyper Page mode, allowing it to access DRAM rows at 1 clock cycle per word (effectively around
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// 17 clks per 16 words, due to required row address loading, probably plus some further minimal overload due to
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// refresh cycles). This is making DMA much faster than CPU memory accesses (CPU DRAM access takes 1 opcode cycle
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// plus 6 waitstates, ie. 7 cycles in total).
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return static_cast<TickCount>(word_count + ((word_count + 15) / 16));
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}
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/// Invalidates any code pages which overlap the specified range.
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ALWAYS_INLINE void InvalidateCodePages(PhysicalMemoryAddress address, u32 word_count)
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{
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const u32 start_page = address / CPU_CODE_CACHE_PAGE_SIZE;
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const u32 end_page = (address + word_count * sizeof(u32)) / CPU_CODE_CACHE_PAGE_SIZE;
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for (u32 page = start_page; page <= end_page; page++)
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{
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if (m_ram_code_bits[page])
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DoInvalidateCodeCache(page);
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}
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}
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CPU::Core* m_cpu = nullptr;
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CPU::CodeCache* m_cpu_code_cache = nullptr;
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DMA* m_dma = nullptr;
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InterruptController* m_interrupt_controller = nullptr;
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GPU* m_gpu = nullptr;
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CDROM* m_cdrom = nullptr;
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Pad* m_pad = nullptr;
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Timers* m_timers = nullptr;
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SPU* m_spu = nullptr;
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MDEC* m_mdec = nullptr;
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SIO* m_sio = nullptr;
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std::array<TickCount, 3> m_exp1_access_time = {};
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std::array<TickCount, 3> m_exp2_access_time = {};
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std::array<TickCount, 3> m_bios_access_time = {};
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std::array<TickCount, 3> m_cdrom_access_time = {};
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std::array<TickCount, 3> m_spu_access_time = {};
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std::bitset<CPU_CODE_CACHE_PAGE_COUNT> m_ram_code_bits{};
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std::array<u8, RAM_SIZE> m_ram{}; // 2MB RAM
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std::array<u8, BIOS_SIZE> m_bios{}; // 512K BIOS ROM
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std::vector<u8> m_exp1_rom;
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MEMCTRL m_MEMCTRL = {};
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u32 m_ram_size_reg = 0;
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std::string m_tty_line_buffer;
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};
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#include "bus.inl"
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