2011-09-14 19:08:43 +00:00
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/**
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** Supermodel
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** A Sega Model 3 Arcade Emulator.
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** Copyright 2011 Bart Trzynadlowski, Nik Henson
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**
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** This file is part of Supermodel.
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**
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** Supermodel is free software: you can redistribute it and/or modify it under
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** the terms of the GNU General Public License as published by the Free
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** Software Foundation, either version 3 of the License, or (at your option)
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** any later version.
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**
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** Supermodel is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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** more details.
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**
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** You should have received a copy of the GNU General Public License along
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** with Supermodel. If not, see <http://www.gnu.org/licenses/>.
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**/
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/*
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* SCSPDSP.cpp
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*
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* SCSP DSP emulation.
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*/
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2011-08-10 04:24:15 +00:00
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#include "Supermodel.h"
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2011-04-24 01:14:00 +00:00
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#include "SCSPDSP.h"
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2011-09-08 05:08:16 +00:00
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//#include <assert.h>
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#define assert(x) ; // disable assert() for releases
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2011-09-14 19:08:43 +00:00
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//#include <memory.h>
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//#include <stdio.h>
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//#include <malloc.h>
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#include <cstdio>
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#include <cstdlib>
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#include <cstring>
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2011-04-24 01:14:00 +00:00
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#pragma warning(disable:4311)
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#define DYNBUF 0x10000
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//this doesn't work at all
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//#define USEFLOATPACK
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//the PACK func in asm plus mov [esi],ax
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unsigned char PackFunc[]={0x8B,0xD8,0xA9,0x00,0x00,0x80,0x00,0x75,0x02,0xF7,0xD3,0xF7,0xD3,0x0F,0xBD,0xCB,
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0xF7,0xD9,0xC1,0xE0,0x08,0x83,0xC1,0x16,0xD3,0xE0,0xC1,0xF8,0x13,0xC1,0xE1,0x0B,
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0x25,0xFF,0x87,0x00,0x00,0x0B,0xC1,0x66,0x89,0x06};
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unsigned char UnpackFunc[]={0x8B,0xD8,0x8B,0xC8,0x81,0xE3,0x00,0x80,0x00,0x00,0x25,0xFF,0x07,
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0x00,0x00,0xC1,0xE9,0x0B,0xC1,0xE0,0x0B,0xC1,0xE3,0x08,0x83,0xE1,0x0F,0x0B,0xC3,
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0xD1,0xEB,0x81,0xF3,0x00,0x00,0x40,0x00,0x0B,0xC3,0x83,0xC1,0x08,0xC1,0xE0,0x08,
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0xD3,0xF8};
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2020-08-22 20:41:47 +00:00
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//#if 0
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//unsigned short inline PACK(signed int val)
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//{
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///* signed int v1=val;
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// int n=0;
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// while(((v1>>22)&1) == ((v1>>23)&1))
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// {
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// v1<<=1;
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// ++n;
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// }
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// v1<<=8;
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// v1>>=11+8;
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// v1=(v1&(~0x7800))|(n<<11);
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// return v1;
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//*/
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//#ifdef USEFLOATPACK
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// unsigned short f;
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// __asm
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// {
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// mov eax,val
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// mov ebx,eax
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// test eax,0x00800000
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// jne negval
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// not ebx
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//negval: not ebx
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// bsr ecx,ebx
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// neg ecx
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// shl eax,8
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// add ecx,22
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// shl eax,cl
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// sar eax,8+11
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// shl ecx,11
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// and eax,~0x7800
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// or eax,ecx
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// mov f,ax
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// }
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// return f;
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//#else
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//
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// //cut to 16 bits
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// unsigned int f=((unsigned int ) val)>>8;
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// return f;
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//#endif
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//}
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//
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//signed int inline UNPACK(unsigned short val)
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//{
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///* if(val)
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// int a=1;
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// unsigned int mant=val&0x7ff;
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// unsigned int exp=(val>>11)&0xf;
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// unsigned int sign=(val>>15)&1;
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// signed int r=0;
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// r|=mant<<11;
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// r|=sign<<23;
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// r|=(sign^1)<<22;
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//
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// //signed int r=val<<8;
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// //if(r&0x00800000)
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// // r|=0xFF000000;
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// r<<=8;
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// r>>=8+exp;
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// return r;
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//*/
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//#ifdef USEFLOATPACK
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// signed int r;
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// __asm
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// {
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// xor eax,eax
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// mov ax,val
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// mov ebx,eax
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// mov ecx,eax
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// and ebx,0x8000
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// and eax,0x07ff
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// shr ecx,11
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// shl eax,11
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// shl ebx,8
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// and ecx,0xF
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// or eax,ebx
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// shr ebx,1
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// xor ebx,0x00400000
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// or eax,ebx
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// add ecx,8
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// shl eax,8
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// sar eax,cl
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// mov r,eax
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// }
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//#else
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// //unpack 16->24
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// signed int r=val<<8;
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// r<<=8;
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// r>>=8;
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//#endif
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// return r;
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//}
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//#else
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static UINT16 PACK(INT32 val)
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2011-04-24 01:14:00 +00:00
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{
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2022-11-08 07:11:14 +00:00
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int sign = (val >> 23) & 0x1;
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UINT32 temp = (val ^ (val << 1)) & 0xFFFFFF;
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int exponent = 0;
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for (int k = 0; k < 12; k++)
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2011-04-24 01:14:00 +00:00
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{
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if (temp & 0x800000)
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break;
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temp <<= 1;
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exponent += 1;
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}
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if (exponent < 12)
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val = (val << exponent) & 0x3FFFFF;
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else
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val <<= 11;
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val >>= 11;
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2020-08-22 20:41:47 +00:00
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val &= 0x7FF;
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2011-04-24 01:14:00 +00:00
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val |= sign << 15;
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val |= exponent << 11;
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2020-08-22 20:41:47 +00:00
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return (UINT16)val;
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2011-04-24 01:14:00 +00:00
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}
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2020-08-22 20:41:47 +00:00
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static INT32 UNPACK(UINT16 val)
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2011-04-24 01:14:00 +00:00
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{
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2022-11-08 07:11:14 +00:00
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int sign = (val >> 15) & 0x1;
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int exponent = (val >> 11) & 0xF;
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int mantissa = val & 0x7FF;
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INT32 uval = mantissa << 11;
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2011-04-24 01:14:00 +00:00
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if (exponent > 11)
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2020-08-22 20:41:47 +00:00
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{
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2011-04-24 01:14:00 +00:00
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exponent = 11;
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2020-08-22 20:41:47 +00:00
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uval |= sign << 22;
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}
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2011-04-24 01:14:00 +00:00
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else
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2020-08-22 20:41:47 +00:00
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{
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2011-04-24 01:14:00 +00:00
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uval |= (sign ^ 1) << 22;
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2020-08-22 20:41:47 +00:00
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}
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2011-04-24 01:14:00 +00:00
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uval |= sign << 23;
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uval <<= 8;
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uval >>= 8;
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uval >>= exponent;
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return uval;
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}
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2020-08-22 20:41:47 +00:00
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//#endif
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2011-04-24 01:14:00 +00:00
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void SCSPDSP_Init(_SCSPDSP *DSP)
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{
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2020-08-22 20:41:47 +00:00
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memset(DSP, 0, sizeof(_SCSPDSP));
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DSP->RBL = (8 * 1024); // Initial RBL is 0
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DSP->Stopped = 1;
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2011-04-24 01:14:00 +00:00
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}
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2020-08-22 20:41:47 +00:00
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//#ifndef DYNDSP
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2011-04-24 01:14:00 +00:00
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void SCSPDSP_Step(_SCSPDSP *DSP)
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{
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2020-08-22 20:41:47 +00:00
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INT32 ACC = 0; //26 bit
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INT32 SHIFTED = 0; //24 bit
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INT32 X = 0; //24 bit
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INT32 Y = 0; //13 bit
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INT32 B = 0; //26 bit
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INT32 INPUTS = 0; //24 bit
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INT32 MEMVAL = 0;
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INT32 FRC_REG = 0; //13 bit
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INT32 Y_REG = 0; //24 bit
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UINT32 ADDR = 0;
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UINT32 ADRS_REG = 0; //13 bit
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int step;
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if (DSP->Stopped)
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2011-04-24 01:14:00 +00:00
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return;
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2020-08-22 20:41:47 +00:00
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memset(DSP->EFREG, 0, 2 * 16);
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for (step = 0; step </*128*/DSP->LastStep; ++step)
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2011-04-24 01:14:00 +00:00
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{
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2020-08-22 20:41:47 +00:00
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UINT16 *IPtr = DSP->MPRO + step * 4;
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// if(IPtr[0]==0 && IPtr[1]==0 && IPtr[2]==0 && IPtr[3]==0)
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// break;
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UINT32 TRA = (IPtr[0] >> 8) & 0x7F;
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UINT32 TWT = (IPtr[0] >> 7) & 0x01;
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UINT32 TWA = (IPtr[0] >> 0) & 0x7F;
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UINT32 XSEL = (IPtr[1] >> 15) & 0x01;
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UINT32 YSEL = (IPtr[1] >> 13) & 0x03;
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UINT32 IRA = (IPtr[1] >> 6) & 0x3F;
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UINT32 IWT = (IPtr[1] >> 5) & 0x01;
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UINT32 IWA = (IPtr[1] >> 0) & 0x1F;
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UINT32 TABLE = (IPtr[2] >> 15) & 0x01;
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UINT32 MWT = (IPtr[2] >> 14) & 0x01;
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UINT32 MRD = (IPtr[2] >> 13) & 0x01;
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UINT32 EWT = (IPtr[2] >> 12) & 0x01;
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UINT32 EWA = (IPtr[2] >> 8) & 0x0F;
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UINT32 ADRL = (IPtr[2] >> 7) & 0x01;
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UINT32 FRCL = (IPtr[2] >> 6) & 0x01;
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UINT32 SHIFT = (IPtr[2] >> 4) & 0x03;
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UINT32 YRL = (IPtr[2] >> 3) & 0x01;
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UINT32 NEGB = (IPtr[2] >> 2) & 0x01;
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UINT32 ZERO = (IPtr[2] >> 1) & 0x01;
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UINT32 BSEL = (IPtr[2] >> 0) & 0x01;
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UINT32 NOFL = (IPtr[3] >> 15) & 0x01; //????
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UINT32 COEF = (IPtr[3] >> 9) & 0x3f;
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UINT32 MASA = (IPtr[3] >> 2) & 0x1f; //???
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UINT32 ADREB = (IPtr[3] >> 1) & 0x01;
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UINT32 NXADR = (IPtr[3] >> 0) & 0x01;
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INT64 v;
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2011-04-24 01:14:00 +00:00
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//operations are done at 24 bit precision
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2020-08-22 20:41:47 +00:00
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#if 0
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if (MASA)
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int a = 1;
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if (NOFL)
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int a = 1;
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#endif
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2011-04-24 01:14:00 +00:00
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//INPUTS RW
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2020-08-22 20:41:47 +00:00
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// colmns97 hits this
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// assert(IRA<0x32);
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if (IRA <= 0x1f)
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INPUTS = DSP->MEMS[IRA];
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else if (IRA <= 0x2F)
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INPUTS = DSP->MIXS[IRA - 0x20] << 4; //MIXS is 20 bit
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else if (IRA <= 0x31)
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INPUTS = DSP->EXTS[IRA - 0x30] << 8; //EXTS is 16 bit
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else
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return;
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2011-04-24 01:14:00 +00:00
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2020-08-22 20:41:47 +00:00
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INPUTS <<= 8;
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INPUTS >>= 8;
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2011-04-24 01:14:00 +00:00
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//if(INPUTS&0x00800000)
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// INPUTS|=0xFF000000;
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2020-08-22 20:41:47 +00:00
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if (IWT)
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2011-04-24 01:14:00 +00:00
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{
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2020-08-22 20:41:47 +00:00
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DSP->MEMS[IWA] = MEMVAL; //MEMVAL was selected in previous MRD
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if (IRA == IWA)
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INPUTS = MEMVAL;
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2011-04-24 01:14:00 +00:00
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}
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//Operand sel
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//B
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2020-08-22 20:41:47 +00:00
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if (!ZERO)
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2011-04-24 01:14:00 +00:00
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{
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2020-08-22 20:41:47 +00:00
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if (BSEL)
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B = ACC;
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2011-04-24 01:14:00 +00:00
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else
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{
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2020-08-22 20:41:47 +00:00
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B = DSP->TEMP[(TRA + DSP->DEC) & 0x7F];
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B <<= 8;
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B >>= 8;
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2011-04-24 01:14:00 +00:00
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//if(B&0x00800000)
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2020-08-22 20:41:47 +00:00
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// B|=0xFF000000; //Sign extend
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2011-04-24 01:14:00 +00:00
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}
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2020-08-22 20:41:47 +00:00
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if (NEGB)
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B = 0 - B;
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2011-04-24 01:14:00 +00:00
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}
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else
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2020-08-22 20:41:47 +00:00
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B = 0;
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2011-04-24 01:14:00 +00:00
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//X
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2020-08-22 20:41:47 +00:00
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if (XSEL)
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X = INPUTS;
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2011-04-24 01:14:00 +00:00
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else
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{
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2020-08-22 20:41:47 +00:00
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X = DSP->TEMP[(TRA + DSP->DEC) & 0x7F];
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X <<= 8;
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X >>= 8;
|
2011-04-24 01:14:00 +00:00
|
|
|
//if(X&0x00800000)
|
|
|
|
// X|=0xFF000000;
|
|
|
|
}
|
|
|
|
|
|
|
|
//Y
|
2020-08-22 20:41:47 +00:00
|
|
|
if (YSEL == 0)
|
|
|
|
Y = FRC_REG;
|
|
|
|
else if (YSEL == 1)
|
|
|
|
Y = DSP->COEF[COEF] >> 3; //COEF is 16 bits
|
|
|
|
else if (YSEL == 2)
|
|
|
|
Y = (Y_REG >> 11) & 0x1FFF;
|
|
|
|
else if (YSEL == 3)
|
|
|
|
Y = (Y_REG >> 4) & 0x0FFF;
|
|
|
|
|
|
|
|
if (YRL)
|
|
|
|
Y_REG = INPUTS;
|
2011-04-24 01:14:00 +00:00
|
|
|
|
|
|
|
//Shifter
|
2020-08-22 20:41:47 +00:00
|
|
|
if (SHIFT == 0)
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
SHIFTED = ACC;
|
|
|
|
if (SHIFTED > 0x007FFFFF)
|
|
|
|
SHIFTED = 0x007FFFFF;
|
|
|
|
if (SHIFTED < (-0x00800000))
|
|
|
|
SHIFTED = -0x00800000;
|
2011-04-24 01:14:00 +00:00
|
|
|
}
|
2020-08-22 20:41:47 +00:00
|
|
|
else if (SHIFT == 1)
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
SHIFTED = ACC * 2;
|
|
|
|
if (SHIFTED > 0x007FFFFF)
|
|
|
|
SHIFTED = 0x007FFFFF;
|
|
|
|
if (SHIFTED < (-0x00800000))
|
|
|
|
SHIFTED = -0x00800000;
|
2011-04-24 01:14:00 +00:00
|
|
|
}
|
2020-08-22 20:41:47 +00:00
|
|
|
else if (SHIFT == 2)
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
SHIFTED = ACC * 2;
|
|
|
|
SHIFTED <<= 8;
|
|
|
|
SHIFTED >>= 8;
|
2011-04-24 01:14:00 +00:00
|
|
|
//SHIFTED&=0x00FFFFFF;
|
|
|
|
//if(SHIFTED&0x00800000)
|
|
|
|
// SHIFTED|=0xFF000000;
|
|
|
|
}
|
2020-08-22 20:41:47 +00:00
|
|
|
else if (SHIFT == 3)
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
SHIFTED = ACC;
|
|
|
|
SHIFTED <<= 8;
|
|
|
|
SHIFTED >>= 8;
|
2011-04-24 01:14:00 +00:00
|
|
|
//SHIFTED&=0x00FFFFFF;
|
|
|
|
//if(SHIFTED&0x00800000)
|
|
|
|
// SHIFTED|=0xFF000000;
|
|
|
|
}
|
|
|
|
|
|
|
|
//ACCUM
|
2020-08-22 20:41:47 +00:00
|
|
|
Y <<= 19;
|
|
|
|
Y >>= 19;
|
2011-04-24 01:14:00 +00:00
|
|
|
//if(Y&0x1000)
|
|
|
|
// Y|=0xFFFFF000;
|
|
|
|
|
2020-08-22 20:41:47 +00:00
|
|
|
v = (((INT64)X*(INT64)Y) >> 12);
|
|
|
|
ACC = (int)v + B;
|
2011-04-24 01:14:00 +00:00
|
|
|
|
2020-08-22 20:41:47 +00:00
|
|
|
if (TWT)
|
|
|
|
DSP->TEMP[(TWA + DSP->DEC) & 0x7F] = SHIFTED;
|
2011-04-24 01:14:00 +00:00
|
|
|
|
2020-08-22 20:41:47 +00:00
|
|
|
if (FRCL)
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
if (SHIFT == 3)
|
|
|
|
FRC_REG = SHIFTED & 0x0FFF;
|
2011-04-24 01:14:00 +00:00
|
|
|
else
|
2020-08-22 20:41:47 +00:00
|
|
|
FRC_REG = (SHIFTED >> 11) & 0x1FFF;
|
2011-04-24 01:14:00 +00:00
|
|
|
}
|
|
|
|
|
2020-08-22 20:41:47 +00:00
|
|
|
if (MRD || MWT)
|
|
|
|
//if(0)
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
ADDR = DSP->MADRS[MASA];
|
|
|
|
if (!TABLE)
|
|
|
|
ADDR += DSP->DEC;
|
|
|
|
if (ADREB)
|
|
|
|
ADDR += ADRS_REG & 0x0FFF;
|
|
|
|
if (NXADR)
|
2011-04-24 01:14:00 +00:00
|
|
|
ADDR++;
|
2020-08-22 20:41:47 +00:00
|
|
|
if (!TABLE)
|
|
|
|
ADDR &= DSP->RBL - 1;
|
2011-04-24 01:14:00 +00:00
|
|
|
else
|
2020-08-22 20:41:47 +00:00
|
|
|
ADDR &= 0xFFFF;
|
2011-04-24 01:14:00 +00:00
|
|
|
//ADDR<<=1;
|
|
|
|
//ADDR+=DSP->RBP<<13;
|
|
|
|
//MEMVAL=DSP->SCSPRAM[ADDR>>1];
|
2020-08-22 20:41:47 +00:00
|
|
|
ADDR += DSP->RBP << 12;
|
2022-11-08 07:11:14 +00:00
|
|
|
if (ADDR > 0x7ffff) ADDR = 0; //!! MAME has ADDR <<= 1 in here, but this seems to be wrong?
|
2020-08-22 20:41:47 +00:00
|
|
|
if (MRD && (step & 1)) //memory only allowed on odd? DoA inserts NOPs on even
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
if (NOFL)
|
|
|
|
MEMVAL = DSP->SCSPRAM[ADDR] << 8;
|
2011-04-24 01:14:00 +00:00
|
|
|
else
|
2020-08-22 20:41:47 +00:00
|
|
|
MEMVAL = UNPACK(DSP->SCSPRAM[ADDR]);
|
2011-04-24 01:14:00 +00:00
|
|
|
}
|
2020-08-22 20:41:47 +00:00
|
|
|
if (MWT && (step & 1))
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
if (NOFL)
|
|
|
|
DSP->SCSPRAM[ADDR] = SHIFTED >> 8;
|
2011-04-24 01:14:00 +00:00
|
|
|
else
|
2020-08-22 20:41:47 +00:00
|
|
|
DSP->SCSPRAM[ADDR] = PACK(SHIFTED);
|
2011-04-24 01:14:00 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-08-22 20:41:47 +00:00
|
|
|
if (ADRL)
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
if (SHIFT == 3)
|
|
|
|
ADRS_REG = (SHIFTED >> 12) & 0xFFF;
|
2011-04-24 01:14:00 +00:00
|
|
|
else
|
2020-08-22 20:41:47 +00:00
|
|
|
ADRS_REG = (INPUTS >> 16);
|
2011-04-24 01:14:00 +00:00
|
|
|
}
|
|
|
|
|
2020-08-22 20:41:47 +00:00
|
|
|
if (EWT)
|
|
|
|
DSP->EFREG[EWA] += SHIFTED >> 8;
|
2011-04-24 01:14:00 +00:00
|
|
|
|
|
|
|
}
|
|
|
|
--DSP->DEC;
|
2020-08-22 20:41:47 +00:00
|
|
|
memset(DSP->MIXS, 0, 4 * 16);
|
2011-04-24 01:14:00 +00:00
|
|
|
}
|
|
|
|
|
2020-08-22 20:41:47 +00:00
|
|
|
void SCSPDSP_SetSample(_SCSPDSP *DSP, INT32 sample, int SEL, int MXL)
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
//DSP->MIXS[SEL]+=sample<<(MXL+1)/*7*/;
|
|
|
|
DSP->MIXS[SEL] += sample;
|
|
|
|
// if(MXL)
|
|
|
|
// int a=1;
|
2011-04-24 01:14:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SCSPDSP_Start(_SCSPDSP *DSP)
|
|
|
|
{
|
|
|
|
int i;
|
2020-08-22 20:41:47 +00:00
|
|
|
DSP->Stopped = 0;
|
|
|
|
for (i = 127; i >= 0; --i)
|
2011-04-24 01:14:00 +00:00
|
|
|
{
|
2020-08-22 20:41:47 +00:00
|
|
|
UINT16 *IPtr = DSP->MPRO + i * 4;
|
2011-04-24 01:14:00 +00:00
|
|
|
|
2020-08-22 20:41:47 +00:00
|
|
|
if (IPtr[0] != 0 || IPtr[1] != 0 || IPtr[2] != 0 || IPtr[3] != 0)
|
2011-04-24 01:14:00 +00:00
|
|
|
break;
|
|
|
|
}
|
2020-08-22 20:41:47 +00:00
|
|
|
DSP->LastStep = i + 1;
|
2011-04-24 01:14:00 +00:00
|
|
|
|
2011-08-09 18:36:29 +00:00
|
|
|
/*
|
2011-04-24 01:14:00 +00:00
|
|
|
int test=0;
|
|
|
|
if(test)
|
|
|
|
{
|
|
|
|
//test
|
|
|
|
FILE *f1;
|
|
|
|
f1=fopen("MPRO","wb");
|
|
|
|
fwrite(DSP->MPRO,128*4*2,1,f1);
|
|
|
|
fwrite(DSP->COEF,64*2,1,f1);
|
|
|
|
fwrite(DSP->MADRS,32*2,1,f1);
|
|
|
|
fclose(f1);
|
|
|
|
}
|
2011-08-09 18:36:29 +00:00
|
|
|
*/
|
2011-04-24 01:14:00 +00:00
|
|
|
|
|
|
|
for(int t=0;t<0x10000;++t)
|
|
|
|
{
|
|
|
|
signed int unp=UNPACK(t);
|
|
|
|
unsigned short t2=PACK(unp);
|
|
|
|
if(t2!=t)
|
|
|
|
int a=1;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef DYNDSP
|
|
|
|
SCSPDSP_Recompile(DSP);
|
|
|
|
#endif
|
|
|
|
}
|