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port some changes from MAME/MESS

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This commit is contained in:
toxieainc 2022-07-18 22:45:23 +02:00 committed by trzy
parent 2df681f009
commit 03002d3f22
1 changed files with 10 additions and 2 deletions
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12
Src/CPU/Z80/Z80.cpp
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@ -2698,7 +2698,7 @@ int CZ80::Run(int numCycles)
break; break;
case 0x71: /* OUT (C),0 */ case 0x71: /* OUT (C),0 */
cycles -= cycleTables[2][0x71]; cycles -= cycleTables[2][0x71];
OUTPUT(lreg(BC), 0); OUTPUT(lreg(BC), lreg(0));
break; break;
case 0x72: /* SBC HL,SP */ case 0x72: /* SBC HL,SP */
cycles -= cycleTables[2][0x72]; cycles -= cycleTables[2][0x72];
@ -2821,6 +2821,8 @@ int CZ80::Run(int numCycles)
cycles -= cycleTables[2][0xB0]; cycles -= cycleTables[2][0xB0];
acu = hreg(AF); acu = hreg(AF);
BC &= 0xffff; BC &= 0xffff;
if (BC == 0)
BC = 0x10000;
do { do {
acu = GetBYTE_pp(HL); acu = GetBYTE_pp(HL);
PutBYTE_pp(DE, acu); PutBYTE_pp(DE, acu);
@ -2832,6 +2834,8 @@ int CZ80::Run(int numCycles)
cycles -= cycleTables[2][0xB1]; cycles -= cycleTables[2][0xB1];
acu = hreg(AF); acu = hreg(AF);
BC &= 0xffff; BC &= 0xffff;
if (BC == 0)
BC = 0x10000;
do { do {
temp = GetBYTE_pp(HL); temp = GetBYTE_pp(HL);
op = --BC != 0; op = --BC != 0;
@ -2868,6 +2872,8 @@ int CZ80::Run(int numCycles)
case 0xB8: /* LDDR */ case 0xB8: /* LDDR */
cycles -= cycleTables[2][0xB8]; cycles -= cycleTables[2][0xB8];
BC &= 0xffff; BC &= 0xffff;
if (BC == 0)
BC = 0x10000;
do { do {
acu = GetBYTE_mm(HL); acu = GetBYTE_mm(HL);
PutBYTE_mm(DE, acu); PutBYTE_mm(DE, acu);
@ -2879,6 +2885,8 @@ int CZ80::Run(int numCycles)
cycles -= cycleTables[2][0xB9]; cycles -= cycleTables[2][0xB9];
acu = hreg(AF); acu = hreg(AF);
BC &= 0xffff; BC &= 0xffff;
if (BC == 0)
BC = 0x10000;
do { do {
temp = GetBYTE_mm(HL); temp = GetBYTE_mm(HL);
op = --BC != 0; op = --BC != 0;
@ -3505,7 +3513,7 @@ int CZ80::Run(int numCycles)
break; break;
case 0xCB: /* CB prefix */ case 0xCB: /* CB prefix */
adr = IY + (signed char) GetBYTE_pp(pc); adr = IY + (signed char) GetBYTE_pp(pc);
adr = adr; //adr = adr;
op = GetBYTE(pc); op = GetBYTE(pc);
cycles -= cycleTables[4][op]; cycles -= cycleTables[4][op];
switch (op & 7) { switch (op & 7) {