From 24d24db988fdf92a8e3368c24384cf84219add9c Mon Sep 17 00:00:00 2001 From: gm-matthew <108370479+gm-matthew@users.noreply.github.com> Date: Sun, 3 Sep 2023 16:51:18 +0100 Subject: [PATCH] Ping-pong flip timing depends of the value of tilegen register 0x08 Also make the debugger display 16 bytes per line when using the "listmemory" command. Mirrored system registers can now be watched --- Src/Debugger/ConsoleDebugger.cpp | 2 +- Src/Debugger/SupermodelDebugger.cpp | 11 ++++++----- Src/Model3/Model3.cpp | 30 ++++++++++++++--------------- 3 files changed, 22 insertions(+), 21 deletions(-) diff --git a/Src/Debugger/ConsoleDebugger.cpp b/Src/Debugger/ConsoleDebugger.cpp index 3e4a892..925819d 100644 --- a/Src/Debugger/ConsoleDebugger.cpp +++ b/Src/Debugger/ConsoleDebugger.cpp @@ -40,7 +40,7 @@ namespace Debugger CConsoleDebugger::CConsoleDebugger() : CDebugger(), m_nextFrame(false), m_listDism(0), m_listMem(0), m_analyseCode(true), m_addrFmt(HexDollar), m_portFmt(Decimal), m_dataFmt(HexDollar), - m_showLabels(true), m_labelsOverAddr(true), m_showOpCodes(false), m_memBytesPerRow(12), m_file(NULL) + m_showLabels(true), m_labelsOverAddr(true), m_showOpCodes(false), m_memBytesPerRow(16), m_file(NULL) { // } diff --git a/Src/Debugger/SupermodelDebugger.cpp b/Src/Debugger/SupermodelDebugger.cpp index f802f55..e7a18f4 100644 --- a/Src/Debugger/SupermodelDebugger.cpp +++ b/Src/Debugger/SupermodelDebugger.cpp @@ -62,8 +62,8 @@ namespace Debugger // Interrupts cpu->AddInterrupt("VD0", 0, "Unknown video-related"); cpu->AddInterrupt("VBL", 1, "VBlank start"); - cpu->AddInterrupt("VD2", 2, "Unknown video-related"); - cpu->AddInterrupt("VD3", 3, "Unknown video-related"); + cpu->AddInterrupt("VDP", 2, "DP done (display processing)"); + cpu->AddInterrupt("VGP", 3, "GP done (geometry processing)"); cpu->AddInterrupt("NET", 4, "Network"); cpu->AddInterrupt("UN5", 5, "Unknown"); cpu->AddInterrupt("SND", 6, "SCSP (sound)"); @@ -82,8 +82,8 @@ namespace Debugger cpu->AddRegion(0xC0000000, 0xC00000FF, false, false, "SCSI (Step 1.x)"); #endif #ifdef NET_BOARD - cpu->AddRegion(0xC0000000, 0xC001FFFF, false, false, "Network Buffer"); - cpu->AddRegion(0xC0020000, 0xC003FFFF, false, false, "Network RAM"); + cpu->AddRegion(0xC0000000, 0xC000FFFF, false, false, "Netboard Shared RAM (Step 1.5+)"); + cpu->AddRegion(0xC0020000, 0xC002FFFF, false, false, "Netboard Program RAM (Step 1.5+)"); #endif cpu->AddRegion(0xC1000000, 0xC10000FF, false, false, "SCSI (Step 1.x) (Lost World expects it here)"); cpu->AddRegion(0xC2000000, 0xC20000FF, false, false, "Real3D DMA (Step 2.x)"); @@ -91,7 +91,7 @@ namespace Debugger cpu->AddRegion(0xF0080000, 0xF0080007, false, false, "Sound Board Registers"); cpu->AddRegion(0xF00C0000, 0xF00DFFFF, false, false, "Backup RAM"); cpu->AddRegion(0xF0100000, 0xF010003F, false, false, "System Registers"); - cpu->AddRegion(0xF0140000, 0xF014003F, false, false, "Real, 0xTime Clock"); + cpu->AddRegion(0xF0140000, 0xF014003F, false, false, "Real-Time Clock"); cpu->AddRegion(0xF0180000, 0xF019FFFF, false, false, "Security Board RAM"); cpu->AddRegion(0xF01A0000, 0xF01A003F, false, false, "Security Board Registers"); cpu->AddRegion(0xF0800CF8, 0xF0800CFF, false, false, "MPC105 CONFIG_cpu->AddR (Step 1.x)"); @@ -103,6 +103,7 @@ namespace Debugger cpu->AddRegion(0xF8FFF000, 0xF8FFF0FF, false, false, "MPC105 (Step 1.x) or MPC106 (Step 2.x) Registers"); cpu->AddRegion(0xF9000000, 0xF90000FF, false, false, "NCR 53C810 Registers (Step 1.x?)"); cpu->AddRegion(0xFE040000, 0xFE04003F, false, false, "Mirrored Input Registers"); + cpu->AddRegion(0xFE100000, 0xFE10003F, false, false, "Mirrored System Registers"); cpu->AddRegion(0xFEC00000, 0xFEDFFFFF, false, false, "MPC106 CONFIG_cpu->AddR (Step 2.x)"); cpu->AddRegion(0xFEE00000, 0xFEFFFFFF, false, false, "MPC106 CONFIG_DATA (Step 2.x)"); cpu->AddRegion(0xFF000000, 0xFF7FFFFF, true, true, "Banked CROM (CROMxx)"); diff --git a/Src/Model3/Model3.cpp b/Src/Model3/Model3.cpp index 20acae9..8769f14 100644 --- a/Src/Model3/Model3.cpp +++ b/Src/Model3/Model3.cpp @@ -48,6 +48,9 @@ * 90000000-9000000B Real3D VROM Texture Port * 94000000-940FFFFF Real3D Texture FIFO * 98000000-980FFFFF Real3D Polygon RAM + * C0000000-C000FFFF Netboard Shared RAM (Step 1.5+) + * C0010000-C00101FF Netboard Registers (Step 1.5+) + * C0020000-C002FFFF Netboard Program RAM (Step 1.5+) * C0000000-C00000FF SCSI (Step 1.x) * C1000000-C10000FF SCSI (Step 1.x) (Lost World expects it here) * C2000000-C20000FF Real3D DMA (Step 2.x) @@ -86,14 +89,14 @@ * F0100014: IRQ Enable * 7 6 5 4 3 2 1 0 * +---+---+---+---+---+---+---+---+ - * | ? |SND| ? |NET|VD3|VD2|VBL|VD0| + * | ? |SND| ? |NET|VGP|VDP|VBL|VD0| * +---+---+---+---+---+---+---+---+ * SND SCSP (sound) * NET Network - * VD3 Unknown video-related - * VD2 Unknown video-related + * VGP GP done (geometry processing) + * VDP DP done (display processing) * VBL VBlank start - * VD0 Unknown video-related (?) + * VD0 Unknown video-related * 0 = Disable, 1 = Enable * * Game Buttons @@ -2042,21 +2045,18 @@ void CModel3::RunMainBoardFrame(void) { UINT32 start = CThread::GetTicks(); - // Compute display and VBlank timings + // Compute display timings unsigned ppcCycles = m_config["PowerPCFrequency"].ValueAs() * 1000000; unsigned frameCycles = (unsigned)((float)ppcCycles / 57.524160f); - unsigned offsetCycles = (unsigned)((float)frameCycles * 33.f / 100.0f); - unsigned dispCycles = frameCycles - offsetCycles; + unsigned lineCycles = frameCycles / 424; + unsigned dispCycles = lineCycles * (TileGen.ReadRegister(0x08) + 40); + unsigned offsetCycles = frameCycles - dispCycles; unsigned statusCycles = (unsigned)((float)frameCycles * (0.005f)); - // we think a frame looks like this on the model 2 - // 66% of frame - // [irq2------------------ping_pong_flips------] - // - // Games will start writing a new frame at the ping_pong time. It could be the buffer swaps here. - // Need more h/w testing to confirm. - // What we are doing here is asserting IRQ2 at 33% of the frame, and treating the ping_pong flip as the front/back buffer swap - // This way the data for the correct frames, ends up in the right frames! + // Games will start writing a new frame after the ping-pong buffers have been flipped, which is indicated by the + // ping-pong status bit. The timing of ping-pong flip is determined by the value of tilegen register 0x08, which + // is the number of active video lines to display before ping-pong flip occurs. Most games set it to 238 or 239 + // so that ping-pong flip occurs 66% of the frame time after IRQ2, though a few games set it to a higher value. // Scale PPC timer ratio according to speed at which the PowerPC is being emulated so that the observed running frequency of the PPC timer // registers is more or less correct. This is needed to get the Virtua Striker 2 series of games running at the right speed (they are