Xargon/Supermodel
1
0
Fork 0
mirror of https://github.com/RetroDECK/Supermodel.git synced 2025-02-16 17:35:39 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Low level z80 core bug

Browse source 
Discovered when looking at lemans ffb board (real Model3 rom, not Model2 stcc one)
This could affect other ffb board and/or scud race DSB1 sound board
However I didn't notice any bad things
This commit is contained in:
SpinDizzy 2020-08-22 09:00:13 +00:00
parent d77433b525
commit 27cda80abb
1 changed files with 21 additions and 21 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

42
Src/CPU/Z80/Z80.cpp
View file

@ -2453,11 +2453,11 @@ int CZ80::Run(int numCycles)
parity(temp);
break;
case 0x41: /* OUT (C),B */
cycles -= cycleTables[2][0x41];
OUTPUT(lreg(BC), BC);
cycles -= cycleTables[2][0x41];
OUTPUT(lreg(BC), hreg(BC));
break;
case 0x42: /* SBC HL,BC */
cycles -= cycleTables[2][0x42];
cycles -= cycleTables[2][0x42];
HL &= 0xffff;
BC &= 0xffff;
sum = HL - BC - TSTFLAG(C);
@ -2504,11 +2504,11 @@ int CZ80::Run(int numCycles)
parity(temp);
break;
case 0x49: /* OUT (C),C */
cycles -= cycleTables[2][0x49];
OUTPUT(lreg(BC), BC);
cycles -= cycleTables[2][0x49];
OUTPUT(lreg(BC), lreg(BC));
break;
case 0x4A: /* ADC HL,BC */
cycles -= cycleTables[2][0x4A];
cycles -= cycleTables[2][0x4A];
HL &= 0xffff;
BC &= 0xffff;
sum = HL + BC + TSTFLAG(C);
@ -2543,11 +2543,11 @@ int CZ80::Run(int numCycles)
parity(temp);
break;
case 0x51: /* OUT (C),D */
cycles -= cycleTables[2][0x51];
OUTPUT(lreg(BC), DE);
cycles -= cycleTables[2][0x51];
OUTPUT(lreg(BC), hreg(DE));
break;
case 0x52: /* SBC HL,DE */
cycles -= cycleTables[2][0x52];
cycles -= cycleTables[2][0x52];
HL &= 0xffff;
DE &= 0xffff;
sum = HL - DE - TSTFLAG(C);
@ -2581,11 +2581,11 @@ int CZ80::Run(int numCycles)
parity(temp);
break;
case 0x59: /* OUT (C),E */
cycles -= cycleTables[2][0x59];
OUTPUT(lreg(BC), DE);
cycles -= cycleTables[2][0x59];
OUTPUT(lreg(BC), lreg(DE));
break;
case 0x5A: /* ADC HL,DE */
cycles -= cycleTables[2][0x5A];
cycles -= cycleTables[2][0x5A];
HL &= 0xffff;
DE &= 0xffff;
sum = HL + DE + TSTFLAG(C);
@ -2619,11 +2619,11 @@ int CZ80::Run(int numCycles)
parity(temp);
break;
case 0x61: /* OUT (C),H */
cycles -= cycleTables[2][0x61];
OUTPUT(lreg(BC), HL);
cycles -= cycleTables[2][0x61];
OUTPUT(lreg(BC), hreg(HL));
break;
case 0x62: /* SBC HL,HL */
cycles -= cycleTables[2][0x62];
cycles -= cycleTables[2][0x62];
HL &= 0xffff;
sum = HL - HL - TSTFLAG(C);
cbits = (HL ^ HL ^ sum) >> 8;
@ -2657,11 +2657,11 @@ int CZ80::Run(int numCycles)
parity(temp);
break;
case 0x69: /* OUT (C),L */
cycles -= cycleTables[2][0x69];
OUTPUT(lreg(BC), HL);
cycles -= cycleTables[2][0x69];
OUTPUT(lreg(BC), lreg(HL));
break;
case 0x6A: /* ADC HL,HL */
cycles -= cycleTables[2][0x6A];
cycles -= cycleTables[2][0x6A];
HL &= 0xffff;
sum = HL + HL + TSTFLAG(C);
cbits = (HL ^ HL ^ sum) >> 8;
@ -2725,11 +2725,11 @@ int CZ80::Run(int numCycles)
parity(temp);
break;
case 0x79: /* OUT (C),A */
cycles -= cycleTables[2][0x79];
OUTPUT(lreg(BC), AF);
cycles -= cycleTables[2][0x79];
OUTPUT(lreg(BC), hreg(AF));
break;
case 0x7A: /* ADC HL,SP */
cycles -= cycleTables[2][0x7A];
cycles -= cycleTables[2][0x7A];
HL &= 0xffff;
SP &= 0xffff;
sum = HL + SP + TSTFLAG(C);