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Low level z80 core bug

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Discovered when looking at lemans ffb board (real Model3 rom, not Model2 stcc one)
This could affect other ffb board and/or scud race DSB1 sound board
However I didn't notice any bad things
This commit is contained in:
SpinDizzy 2020-08-22 09:00:13 +00:00
parent d77433b525
commit 27cda80abb
1 changed files with 21 additions and 21 deletions

42
Src/CPU/Z80/Z80.cpp
View file

@ -2453,11 +2453,11 @@ int CZ80::Run(int numCycles)
parity(temp); parity(temp);
break; break;
case 0x41: /* OUT (C),B */ case 0x41: /* OUT (C),B */
cycles -= cycleTables[2][0x41]; cycles -= cycleTables[2][0x41];
OUTPUT(lreg(BC), BC); OUTPUT(lreg(BC), hreg(BC));
break; break;
case 0x42: /* SBC HL,BC */ case 0x42: /* SBC HL,BC */
cycles -= cycleTables[2][0x42]; cycles -= cycleTables[2][0x42];
HL &= 0xffff; HL &= 0xffff;
BC &= 0xffff; BC &= 0xffff;
sum = HL - BC - TSTFLAG(C); sum = HL - BC - TSTFLAG(C);
@ -2504,11 +2504,11 @@ int CZ80::Run(int numCycles)
parity(temp); parity(temp);
break; break;
case 0x49: /* OUT (C),C */ case 0x49: /* OUT (C),C */
cycles -= cycleTables[2][0x49]; cycles -= cycleTables[2][0x49];
OUTPUT(lreg(BC), BC); OUTPUT(lreg(BC), lreg(BC));
break; break;
case 0x4A: /* ADC HL,BC */ case 0x4A: /* ADC HL,BC */
cycles -= cycleTables[2][0x4A]; cycles -= cycleTables[2][0x4A];
HL &= 0xffff; HL &= 0xffff;
BC &= 0xffff; BC &= 0xffff;
sum = HL + BC + TSTFLAG(C); sum = HL + BC + TSTFLAG(C);
@ -2543,11 +2543,11 @@ int CZ80::Run(int numCycles)
parity(temp); parity(temp);
break; break;
case 0x51: /* OUT (C),D */ case 0x51: /* OUT (C),D */
cycles -= cycleTables[2][0x51]; cycles -= cycleTables[2][0x51];
OUTPUT(lreg(BC), DE); OUTPUT(lreg(BC), hreg(DE));
break; break;
case 0x52: /* SBC HL,DE */ case 0x52: /* SBC HL,DE */
cycles -= cycleTables[2][0x52]; cycles -= cycleTables[2][0x52];
HL &= 0xffff; HL &= 0xffff;
DE &= 0xffff; DE &= 0xffff;
sum = HL - DE - TSTFLAG(C); sum = HL - DE - TSTFLAG(C);
@ -2581,11 +2581,11 @@ int CZ80::Run(int numCycles)
parity(temp); parity(temp);
break; break;
case 0x59: /* OUT (C),E */ case 0x59: /* OUT (C),E */
cycles -= cycleTables[2][0x59]; cycles -= cycleTables[2][0x59];
OUTPUT(lreg(BC), DE); OUTPUT(lreg(BC), lreg(DE));
break; break;
case 0x5A: /* ADC HL,DE */ case 0x5A: /* ADC HL,DE */
cycles -= cycleTables[2][0x5A]; cycles -= cycleTables[2][0x5A];
HL &= 0xffff; HL &= 0xffff;
DE &= 0xffff; DE &= 0xffff;
sum = HL + DE + TSTFLAG(C); sum = HL + DE + TSTFLAG(C);
@ -2619,11 +2619,11 @@ int CZ80::Run(int numCycles)
parity(temp); parity(temp);
break; break;
case 0x61: /* OUT (C),H */ case 0x61: /* OUT (C),H */
cycles -= cycleTables[2][0x61]; cycles -= cycleTables[2][0x61];
OUTPUT(lreg(BC), HL); OUTPUT(lreg(BC), hreg(HL));
break; break;
case 0x62: /* SBC HL,HL */ case 0x62: /* SBC HL,HL */
cycles -= cycleTables[2][0x62]; cycles -= cycleTables[2][0x62];
HL &= 0xffff; HL &= 0xffff;
sum = HL - HL - TSTFLAG(C); sum = HL - HL - TSTFLAG(C);
cbits = (HL ^ HL ^ sum) >> 8; cbits = (HL ^ HL ^ sum) >> 8;
@ -2657,11 +2657,11 @@ int CZ80::Run(int numCycles)
parity(temp); parity(temp);
break; break;
case 0x69: /* OUT (C),L */ case 0x69: /* OUT (C),L */
cycles -= cycleTables[2][0x69]; cycles -= cycleTables[2][0x69];
OUTPUT(lreg(BC), HL); OUTPUT(lreg(BC), lreg(HL));
break; break;
case 0x6A: /* ADC HL,HL */ case 0x6A: /* ADC HL,HL */
cycles -= cycleTables[2][0x6A]; cycles -= cycleTables[2][0x6A];
HL &= 0xffff; HL &= 0xffff;
sum = HL + HL + TSTFLAG(C); sum = HL + HL + TSTFLAG(C);
cbits = (HL ^ HL ^ sum) >> 8; cbits = (HL ^ HL ^ sum) >> 8;
@ -2725,11 +2725,11 @@ int CZ80::Run(int numCycles)
parity(temp); parity(temp);
break; break;
case 0x79: /* OUT (C),A */ case 0x79: /* OUT (C),A */
cycles -= cycleTables[2][0x79]; cycles -= cycleTables[2][0x79];
OUTPUT(lreg(BC), AF); OUTPUT(lreg(BC), hreg(AF));
break; break;
case 0x7A: /* ADC HL,SP */ case 0x7A: /* ADC HL,SP */
cycles -= cycleTables[2][0x7A]; cycles -= cycleTables[2][0x7A];
HL &= 0xffff; HL &= 0xffff;
SP &= 0xffff; SP &= 0xffff;
sum = HL + SP + TSTFLAG(C); sum = HL + SP + TSTFLAG(C);