mirror of
https://github.com/RetroDECK/Supermodel.git
synced 2024-11-22 22:05:38 +00:00
Added 8- and 16-bit tilegen VRAM access handlers to fix missing columns in Star Wars Trilogy tilemaps. Thanks to Spindizzi for initial confirmation that this was the problem.
This commit is contained in:
Bart Trzynadlowski
parent
9fb6acc92d
commit
61159c07f8
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@ -858,19 +858,12 @@ void CModel3::WriteSystemRegister(unsigned reg, UINT8 data)
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/******************************************************************************
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/******************************************************************************
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Optimized Address Space Access Handlers
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Address Space Access Handlers
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Although I have not yet profiled the code, these ought to be more optimal,
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especially if the compiler can generate jump tables.
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NOTE: Testing of some of the address ranges is not strict enough, especially
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NOTE: Testing of some of the address ranges is not strict enough, especially
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for the MPC10x. Write32() handles the MPC10x most correctly. For now,
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for the MPC10x. Write32() handles the MPC10x most correctly.
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accesses outside of the handled ranges have not been observed. Use the DEBUG
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version of these handlers for validation of new games.
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******************************************************************************/
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******************************************************************************/
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#ifndef DEBUG
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/*
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/*
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* CModel3::Read8(addr):
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* CModel3::Read8(addr):
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* CModel3::Read16(addr):
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* CModel3::Read16(addr):
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@ -936,6 +929,15 @@ UINT8 CModel3::Read8(UINT32 addr)
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break;
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break;
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// Tile generator
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case 0xF1:
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if (addr < 0xF1120000)
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{
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// Tile generator accesses its RAM as little endian, no adjustment needed here
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return TileGen.ReadRAM8(addr&0x1FFFFF);
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}
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break;
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// 53C810 SCSI
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// 53C810 SCSI
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case 0xC0: // only on Step 1.0
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case 0xC0: // only on Step 1.0
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if (Game->step != 0x10)
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if (Game->step != 0x10)
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@ -1024,6 +1026,16 @@ UINT16 CModel3::Read16(UINT32 addr)
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break;
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break;
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// Tile generator
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case 0xF1:
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if (addr < 0xF1120000)
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{
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// Tile generator accesses its RAM as little endian, no adjustment needed here
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uint16_t data = TileGen.ReadRAM16(addr&0x1FFFFF);
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return FLIPENDIAN16(data);
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}
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break;
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// Unknown
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// Unknown
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default:
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default:
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break;
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break;
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@ -1149,7 +1161,7 @@ UINT32 CModel3::Read32(UINT32 addr)
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// Tile generator accesses its RAM as little endian, must flip for big endian PowerPC
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// Tile generator accesses its RAM as little endian, must flip for big endian PowerPC
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if (addr < 0xF1120000)
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if (addr < 0xF1120000)
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{
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{
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data = TileGen.ReadRAM(addr&0x1FFFFF);
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data = TileGen.ReadRAM32(addr&0x1FFFFF);
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return FLIPENDIAN32(data);
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return FLIPENDIAN32(data);
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}
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}
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else if ((addr>=0xF1180000) && (addr<0xF1180100))
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else if ((addr>=0xF1180000) && (addr<0xF1180100))
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@ -1262,6 +1274,16 @@ void CModel3::Write8(UINT32 addr, UINT8 data)
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DebugLog("PC=%08X\twrite8 : %08X=%02X\n", ppc_get_pc(), addr, data);
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DebugLog("PC=%08X\twrite8 : %08X=%02X\n", ppc_get_pc(), addr, data);
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break;
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break;
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// Tile generator
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case 0xF1:
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if (addr < 0xF1120000)
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{
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// Tile generator accesses its RAM as little endian, no adjustment needed here
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TileGen.WriteRAM8(addr&0x1FFFFF, data);
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break;
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}
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goto Unknown8;
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// MPC105/106
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// MPC105/106
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case 0xF8:
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case 0xF8:
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PCIBridge.WriteRegister(addr&0xFF,data);
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PCIBridge.WriteRegister(addr&0xFF,data);
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@ -1333,6 +1355,15 @@ void CModel3::Write16(UINT32 addr, UINT16 data)
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DebugLog("PC=%08X\twrite16 : %08X=%04X\n", ppc_get_pc(), addr, data);
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DebugLog("PC=%08X\twrite16 : %08X=%04X\n", ppc_get_pc(), addr, data);
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break;
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break;
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// Tile generator
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case 0xF1:
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if (addr < 0xF1120000)
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{
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// Tile generator accesses its RAM as little endian, no adjustment needed here
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TileGen.WriteRAM16(addr&0x1FFFFF, FLIPENDIAN16(data));
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}
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goto Unknown16;
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// MPC105/106
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// MPC105/106
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case 0xF8:
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case 0xF8:
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// Write in big endian order, like a real PowerPC
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// Write in big endian order, like a real PowerPC
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@ -1342,6 +1373,7 @@ void CModel3::Write16(UINT32 addr, UINT16 data)
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// Unknown
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// Unknown
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default:
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default:
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Unknown16:
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DebugLog("PC=%08X\twrite16: %08X=%04X\n", ppc_get_pc(), addr, data);
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DebugLog("PC=%08X\twrite16: %08X=%04X\n", ppc_get_pc(), addr, data);
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break;
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break;
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}
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}
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@ -1349,9 +1381,6 @@ void CModel3::Write16(UINT32 addr, UINT16 data)
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void CModel3::Write32(UINT32 addr, UINT32 data)
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void CModel3::Write32(UINT32 addr, UINT32 data)
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{
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{
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// Debugging VF3 missing stage textures
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//if ((addr == 0xb4000)) printf("B4000 written @ pc=%08x lr=%08x\n", ppc_get_pc(), ppc_get_lr());
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if ((addr&3))
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if ((addr&3))
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{
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{
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Write16(addr+0,data>>16);
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Write16(addr+0,data>>16);
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@ -1502,7 +1531,7 @@ void CModel3::Write32(UINT32 addr, UINT32 data)
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{
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{
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// Tile generator accesses its RAM as little endian, must flip for big endian PowerPC
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// Tile generator accesses its RAM as little endian, must flip for big endian PowerPC
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data = FLIPENDIAN32(data);
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data = FLIPENDIAN32(data);
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TileGen.WriteRAM(addr&0x1FFFFF,data);
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TileGen.WriteRAM32(addr&0x1FFFFF,data);
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break;
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break;
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}
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}
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else if ((addr>=0xF1180000) && (addr<0xF1180100))
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else if ((addr>=0xF1180000) && (addr<0xF1180100))
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@ -1549,344 +1578,6 @@ void CModel3::Write64(UINT32 addr, UINT64 data)
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Write32(addr+4, (UINT32) data);
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Write32(addr+4, (UINT32) data);
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}
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}
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#endif
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/******************************************************************************
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Debug Mode (Strict) Address Space Access Handlers
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Enabled only if DEBUG is defined. These perform stricter checks than the
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"optimized" handlers but may be slower.
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******************************************************************************/
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#ifdef DEBUG
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/*
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* CModel3::Read8(addr):
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* CModel3::Read16(addr):
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* CModel3::Read32(addr):
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* CModel3::Read64(addr):
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*
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* Read handlers.
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*/
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UINT8 CModel3::Read8(UINT32 addr)
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{
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if (addr<0x00800000)
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return ram[addr^3];
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else if ((addr>=0xFF000000) && (addr<0xFF800000))
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return cromBank[(addr&0x7FFFFF)^3];
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else if (addr>=0xFF800000)
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return crom[(addr&0x7FFFFF)^3];
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else if ((addr>=0xC2000000) && (addr<0xC2000100))
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return GPU.ReadDMARegister8(addr&0xFF);
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else if (((addr>=0xF0040000) && (addr<0xF0040040)) || ((addr>=0xFE040000) && (addr<0xFE040040)))
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return ReadInputs(addr&0x3F);
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else if (((addr>=0xF0080000) && (addr<=0xF0080007)) || ((addr>=0xFE080000) && (addr<=0xFE080007)))
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{
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if ((addr&0xF) == 4) // MIDI control port
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return 0xFF;
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}
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else if (((addr>=0xF00C0000) && (addr<0xF00DFFFF)) || ((addr>=0xFE0C0000) && (addr<0xFE0DFFFF)))
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return backupRAM[(addr&0x1FFFF)^3];
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else if (((addr>=0xF0100000) && (addr<0xF0100040)) || ((addr>=0xFE100000) && (addr<0xFE100040)))
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return ReadSystemRegister(addr&0x3F);
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else if (((addr>=0xF0140000) && (addr<0xF0140040)) || ((addr>=0xFE140000) && (addr<0xFE140040)))
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{
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if ((addr&3)==1) // battery voltage test
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return 0x03;
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else if ((addr&3)==0)
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return RTC.ReadRegister((addr>>2)&0xF);
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return 0;
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}
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else if (((addr>=0xF9000000) && (addr<0xF9000100)) || ((addr>=0xC1000000) && (addr<0xC1000100)) || ((Game->step==0x10) && ((addr>=0xC0000000) && (addr<0xC0000100))))
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return SCSI.ReadRegister(addr&0xFF);
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DebugLog("PC=%08X\tread8 : %08X\n", ppc_get_pc(), addr);
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return 0xFF;
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}
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UINT16 CModel3::Read16(UINT32 addr)
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{
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UINT16 data;
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if ((addr&1))
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{
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data = Read8(addr+0)<<8;
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data |= Read8(addr+1);
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return data;
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}
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if (addr<0x00800000)
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return *(UINT16 *) &ram[addr^2];
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else if ((addr>=0xFF000000) && (addr<0xFF800000))
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return *(UINT16 *) &cromBank[(addr&0x7FFFFF)^2];
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else if (addr>=0xFF800000)
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return *(UINT16 *) &crom[(addr&0x7FFFFF)^2];
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else if (((addr>=0xF00C0000) && (addr<0xF00DFFFF)) || ((addr>=0xFE0C0000) && (addr<0xFE0DFFFF)))
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return *(UINT16 *) &backupRAM[(addr&0x1FFFF)^2];
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else if ((addr>=0xF0C00CF8) && (addr<0xF0C00D00)) // MPC105
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return PCIBridge.ReadPCIConfigData(16,addr&3);
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else if ((addr>=0xFEE00000) && (addr<0xFEF00000)) // MPC106
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return PCIBridge.ReadPCIConfigData(16,addr&3);
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DebugLog("PC=%08X\tread16: %08X\n", ppc_get_pc(), addr);
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return 0xFFFF;
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}
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UINT32 CModel3::Read32(UINT32 addr)
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{
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UINT32 data;
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if ((addr&3))
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{
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data = Read16(addr+0)<<16;
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data |= Read16(addr+2);
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return data;
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}
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if (addr<0x00800000)
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return *(UINT32 *) &ram[addr];
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else if ((addr>=0xFF000000) && (addr<0xFF800000))
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return *(UINT32 *) &cromBank[(addr&0x7FFFFF)];
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else if (addr>=0xFF800000)
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return *(UINT32 *) &crom[(addr&0x7FFFFF)];
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else if ((addr>=0x84000000) && (addr<0x8400003F))
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return GPU.ReadRegister(addr&0x3F);
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else if ((addr>=0xC2000000) && (addr<0xC2000100))
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{
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data = GPU.ReadDMARegister32(addr&0xFF);
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return FLIPENDIAN32(data);
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}
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else if (((addr>=0xF0040000) && (addr<0xF0040040)) || ((addr>=0xFE040000) && (addr<0xFE040040)))
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{
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data = ReadInputs((addr&0x3F)+0) << 24;
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data |= ReadInputs((addr&0x3F)+1) << 16;
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data |= ReadInputs((addr&0x3F)+2) << 8;
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data |= ReadInputs((addr&0x3F)+3) << 0;
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return data;
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}
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else if (((addr>=0xF00C0000) && (addr<0xF00DFFFF)) || ((addr>=0xFE0C0000) && (addr<0xFE0DFFFF)))
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return *(UINT32 *) &backupRAM[(addr&0x1FFFF)];
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else if (((addr>=0xF0100000) && (addr<0xF0100040)) || ((addr>=0xFE100000) && (addr<0xFE100040)))
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{
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data = ReadSystemRegister((addr&0x3F)+0) << 24;
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data |= ReadSystemRegister((addr&0x3F)+1) << 16;
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data |= ReadSystemRegister((addr&0x3F)+2) << 8;
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data |= ReadSystemRegister((addr&0x3F)+3) << 0;
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return data;
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}
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else if ((addr>=0xF0C00CF8) && (addr<0xF0C00D00)) // MPC105
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return PCIBridge.ReadPCIConfigData(32,0);
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else if ((addr>=0xFEE00000) && (addr<0xFEF00000)) // MPC106
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return PCIBridge.ReadPCIConfigData(32,0);
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else if (((addr>=0xF0140000) && (addr<0xF0140040)) || ((addr>=0xFE140000) && (addr<0xFE140040)))
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{
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data = (RTC.ReadRegister((addr>>2)&0xF) << 24);
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data |= 0x00030000; // set these bits to pass battery voltage test
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return data;
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}
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else if (((addr>=0xF0180000) && (addr<0xF019FFFF)) || ((addr>=0xFE180000) && (addr<0xFE19FFFF)))
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return *(UINT32 *) &securityRAM[(addr&0x1FFFF)]; // so far, only 32-bit access observed, so we use little endian access
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else if (((addr>=0xF01A0000) && (addr<0xF01A003F)) || ((addr>=0xFE1A0000) && (addr<0xFE1A003F)))
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return ReadSecurity(addr&0x3F);
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else if ((addr>=0xF1000000) && (addr<0xF1120000))
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{
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// Tile generator accesses its RAM as little endian, must flip for big endian PowerPC
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data = TileGen.ReadRAM(addr&0x1FFFFF);
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return FLIPENDIAN32(data);
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}
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else if (((addr>=0xF9000000) && (addr<0xF9000100)) || ((addr>=0xC1000000) && (addr<0xC1000100)) || ((Game->step==0x10) && ((addr>=0xC0000000) && (addr<0xC0000100))))
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{
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data = (SCSI.ReadRegister((addr+0)&0xFF) << 24);
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data |= (SCSI.ReadRegister((addr+1)&0xFF) << 16);
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data |= (SCSI.ReadRegister((addr+2)&0xFF) << 8);
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data |= (SCSI.ReadRegister((addr+3)&0xFF) << 0);
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return data;
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}
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// FIXES 2D GRAPHICS (to-do: integrate this into tilegen.cpp)
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if (addr==0xF1180000)
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return 0;
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DebugLog("PC=%08X\tread32: %08X\n", ppc_get_pc(), addr);
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return 0xFFFFFFFF;
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}
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UINT64 CModel3::Read64(UINT32 addr)
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{
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UINT64 data;
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data = Read32(addr+0);
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data <<= 32;
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data |= Read32(addr+4);
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return data;
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}
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/*
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* CModel3::Write8(addr, data):
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* CModel3::Write16(addr, data):
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* CModel3::Write32(addr, data):
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* CModel3::Write64(addr, data):
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*
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* Write handlers.
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*/
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void CModel3::Write8(UINT32 addr, UINT8 data)
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{
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if (addr<0x00800000)
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ram[addr^3] = data;
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else if ((addr>=0xC2000000) && (addr<0xC2000100))
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GPU.WriteDMARegister8(addr&0xFF,data);
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else if (((addr>=0xF0040000) && (addr<0xF0040040)) || ((addr>=0xFE040000) && (addr<0xFE040040)))
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WriteInputs(addr&0x3F,data);
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else if (((addr>=0xF0080000) && (addr<=0xF0080007)) || ((addr>=0xFE080000) && (addr<=0xFE080007)))
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{
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if ((addr&0xF) == 0) // MIDI data port
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SoundBoard.WriteMIDIPort(data);
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else if ((addr&0xF) == 4) // MIDI control port
|
|
||||||
midiCtrlPort = data;
|
|
||||||
}
|
|
||||||
else if (((addr>=0xF00C0000) && (addr<0xF00E0000)) || ((addr>=0xFE0C0000) && (addr<0xFE0E0000)))
|
|
||||||
backupRAM[(addr&0x1FFFF)^3] = data;
|
|
||||||
else if (((addr>=0xF0100000) && (addr<0xF0100040)) || ((addr>=0xFE100000) && (addr<0xFE100040)))
|
|
||||||
WriteSystemRegister(addr&0x3F,data);
|
|
||||||
else if (((addr>=0xF0140000) && (addr<0xF0140040)) || ((addr>=0xFE140000) && (addr<0xFE140040)))
|
|
||||||
{
|
|
||||||
if ((addr&3)==0)
|
|
||||||
RTC.WriteRegister((addr>>2)&0xF,data);
|
|
||||||
}
|
|
||||||
else if ((addr>=0xF8FFF000) && (addr<0xF8FFF100))
|
|
||||||
PCIBridge.WriteRegister(addr&0xFF,data);
|
|
||||||
else if (((addr>=0xF9000000) && (addr<0xF9000100)) || ((addr>=0xC1000000) && (addr<0xC1000100)) || ((Game->step==0x10) && ((addr>=0xC0000000) && (addr<0xC0000100))))
|
|
||||||
SCSI.WriteRegister(addr&0xFF,data);
|
|
||||||
else
|
|
||||||
{
|
|
||||||
DebugLog("PC=%08X\twrite8 : %08X=%02X\n", ppc_get_pc(), addr, data);
|
|
||||||
//printf("PC=%08X\twrite8 : %08X=%02X\n", ppc_get_pc(), addr, data);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void CModel3::Write16(UINT32 addr, UINT16 data)
|
|
||||||
{
|
|
||||||
if ((addr&1))
|
|
||||||
{
|
|
||||||
Write8(addr+0,data>>8);
|
|
||||||
Write8(addr+1,data&0xFF);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (addr<0x00800000)
|
|
||||||
*(UINT16 *) &ram[addr^2] = data;
|
|
||||||
else if (((addr>=0xF00C0000) && (addr<0xF00E0000)) || ((addr>=0xFE0C0000) && (addr<0xFE0E0000)))
|
|
||||||
*(UINT16 *) &backupRAM[(addr&0x1FFFF)^2] = data;
|
|
||||||
else if ((addr>=0xF0C00CF8) && (addr<0xF0C00D00))
|
|
||||||
PCIBridge.WritePCIConfigData(16,addr&2,data);
|
|
||||||
else if ((addr>=0xF8FFF000) && (addr<0xF8FFF100))
|
|
||||||
{
|
|
||||||
// Write in big endian order, like a real PowerPC
|
|
||||||
PCIBridge.WriteRegister((addr&0xFF)+0,data>>8);
|
|
||||||
PCIBridge.WriteRegister((addr&0xFF)+1,data&0xFF);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
DebugLog("PC=%08X\twrite16: %08X=%04X\n", ppc_get_pc(), addr, data);
|
|
||||||
//printf("PC=%08X\twrite16: %08X=%04X\n", ppc_get_pc(), addr, data);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void CModel3::Write32(UINT32 addr, UINT32 data)
|
|
||||||
{
|
|
||||||
if ((addr&3))
|
|
||||||
{
|
|
||||||
Write16(addr+0,data>>16);
|
|
||||||
Write16(addr+2,data);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (addr<0x00800000)
|
|
||||||
*(UINT32 *) &ram[addr] = data;
|
|
||||||
else if ((addr>=0x88000000) && (addr<0x88000008))
|
|
||||||
GPU.Flush();
|
|
||||||
else if ((addr>=0x8C000000) && (addr<0x8C400000))
|
|
||||||
GPU.WriteLowCullingRAM(addr&0x3FFFFF,FLIPENDIAN32(data));
|
|
||||||
else if ((addr>=0x8E000000) && (addr<0x8E100000))
|
|
||||||
GPU.WriteHighCullingRAM(addr&0xFFFFF,FLIPENDIAN32(data));
|
|
||||||
else if ((addr>=0x90000000) && (addr<0x90000018))
|
|
||||||
GPU.WriteTexturePort(addr&0xFF,FLIPENDIAN32(data));
|
|
||||||
else if ((addr>=0x94000000) && (addr<0x94100000))
|
|
||||||
GPU.WriteTextureFIFO(FLIPENDIAN32(data));
|
|
||||||
else if ((addr>=0x98000000) && (addr<0x98400000))
|
|
||||||
GPU.WritePolygonRAM(addr&0x3FFFFF,FLIPENDIAN32(data));
|
|
||||||
else if ((addr>=0xC2000000) && (addr<0xC2000100))
|
|
||||||
GPU.WriteDMARegister32(addr&0xFF,FLIPENDIAN32(data));
|
|
||||||
else if (((addr>=0xF0040000) && (addr<0xF0040040)) || ((addr>=0xFE040000) && (addr<0xFE040040)))
|
|
||||||
{
|
|
||||||
WriteInputs((addr&0x3F)+0,(data>>24)&0xFF);
|
|
||||||
WriteInputs((addr&0x3F)+1,(data>>16)&0xFF);
|
|
||||||
WriteInputs((addr&0x3F)+2,(data>>8)&0xFF);
|
|
||||||
WriteInputs((addr&0x3F)+3,(data>>0)&0xFF);
|
|
||||||
}
|
|
||||||
else if (((addr>=0xF00C0000) && (addr<0xF00E0000)) || ((addr>=0xFE0C0000) && (addr<0xFE0E0000)))
|
|
||||||
*(UINT32 *) &backupRAM[(addr&0x1FFFF)] = data;
|
|
||||||
else if ((addr>=0xF0800CF8) && (addr<0xF0800D00)) // MPC105
|
|
||||||
PCIBridge.WritePCIConfigAddress(data);
|
|
||||||
else if ((addr>=0xF0C00CF8) && (addr<0xF0C00D00)) // MPC105
|
|
||||||
PCIBridge.WritePCIConfigData(32,0,data);
|
|
||||||
else if ((addr>=0xFEC00000) && (addr<0xFEE00000)) // MPC106
|
|
||||||
PCIBridge.WritePCIConfigAddress(data);
|
|
||||||
else if ((addr>=0xFEE00000) && (addr<0xFEF00000)) // MPC106
|
|
||||||
PCIBridge.WritePCIConfigData(32,0,data);
|
|
||||||
else if (((addr>=0xF0100000) && (addr<0xF0100040)) || ((addr>=0xFE100000) && (addr<0xFE100040)))
|
|
||||||
{
|
|
||||||
WriteSystemRegister((addr&0x3F)+0,(data>>24)&0xFF);
|
|
||||||
WriteSystemRegister((addr&0x3F)+1,(data>>16)&0xFF);
|
|
||||||
WriteSystemRegister((addr&0x3F)+2,(data>>8)&0xFF);
|
|
||||||
WriteSystemRegister((addr&0x3F)+3,(data>>0)&0xFF);
|
|
||||||
}
|
|
||||||
else if (((addr>=0xF0140000) && (addr<0xF0140040)) || ((addr>=0xFE140000) && (addr<0xFE140040)))
|
|
||||||
RTC.WriteRegister((addr>>2)&0xF,data);
|
|
||||||
else if (((addr>=0xF0180000) && (addr<0xF019FFFF)) || ((addr>=0xFE180000) && (addr<0xFE19FFFF)))
|
|
||||||
*(UINT32 *) &securityRAM[(addr&0x1FFFF)] = data; // so far, only 32-bit access observed, so just store little endian
|
|
||||||
else if (((addr>=0xF01A0000) && (addr<0xF01A003F)) || ((addr>=0xFE1A0000) && (addr<0xFE1A003F)))
|
|
||||||
WriteSecurity(addr&0x3F,data);
|
|
||||||
else if ((addr>=0xF1000000) && (addr<0xF1120000))
|
|
||||||
{
|
|
||||||
// Tile generator accesses its RAM as little endian, must flip for big endian PowerPC
|
|
||||||
data = FLIPENDIAN32(data);
|
|
||||||
TileGen.WriteRAM(addr&0x1FFFFF,data);
|
|
||||||
}
|
|
||||||
else if ((addr>=0xF1180000) && (addr<0xF1180100))
|
|
||||||
TileGen.WriteRegister(addr&0xFF,FLIPENDIAN32(data));
|
|
||||||
else if ((addr>=0xF8FFF000) && (addr<0xF8FFF100))
|
|
||||||
{
|
|
||||||
// Write in big endian order, like a real PowerPC
|
|
||||||
PCIBridge.WriteRegister((addr&0xFF)+0,(data>>24)&0xFF);
|
|
||||||
PCIBridge.WriteRegister((addr&0xFF)+1,(data>>16)&0xFF);
|
|
||||||
PCIBridge.WriteRegister((addr&0xFF)+2,(data>>8)&0xFF);
|
|
||||||
PCIBridge.WriteRegister((addr&0xFF)+3,data&0xFF);
|
|
||||||
}
|
|
||||||
else if (((addr>=0xF9000000) && (addr<0xF9000100)) || ((addr>=0xC1000000) && (addr<0xC1000100)) || ((Game->step==0x10) && ((addr>=0xC0000000) && (addr<0xC0000100))))
|
|
||||||
{
|
|
||||||
SCSI.WriteRegister((addr&0xFF)+0,(data>>24)&0xFF);
|
|
||||||
SCSI.WriteRegister((addr&0xFF)+1,(data>>16)&0xFF);
|
|
||||||
SCSI.WriteRegister((addr&0xFF)+2,(data>>8)&0xFF);
|
|
||||||
SCSI.WriteRegister((addr&0xFF)+3,data&0xFF);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
//printf("%08X=%08X\n", addr, data);
|
|
||||||
DebugLog("PC=%08X\twrite32: %08X=%08X\n", ppc_get_pc(), addr, data);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void CModel3::Write64(UINT32 addr, UINT64 data)
|
|
||||||
{
|
|
||||||
Write32(addr+0, (UINT32) (data>>32));
|
|
||||||
Write32(addr+4, (UINT32) data);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/******************************************************************************
|
/******************************************************************************
|
||||||
Emulation and Interface Functions
|
Emulation and Interface Functions
|
||||||
|
|
|
||||||
|
|
@ -103,7 +103,7 @@ void CTileGen::LoadState(CBlockFile *SaveState)
|
||||||
UINT32 data;
|
UINT32 data;
|
||||||
|
|
||||||
SaveState->Read(&data, sizeof(data));
|
SaveState->Read(&data, sizeof(data));
|
||||||
WriteRAM(i, data);
|
WriteRAM32(i, data);
|
||||||
}
|
}
|
||||||
SaveState->Read(regs, sizeof(regs));
|
SaveState->Read(regs, sizeof(regs));
|
||||||
|
|
||||||
|
|
@ -267,12 +267,12 @@ void CTileGen::EndFrame(void)
|
||||||
Emulation Functions
|
Emulation Functions
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
||||||
UINT32 CTileGen::ReadRAM(unsigned addr)
|
UINT32 CTileGen::ReadRAM32(unsigned addr)
|
||||||
{
|
{
|
||||||
return *(UINT32 *) &vram[addr];
|
return *(UINT32 *) &vram[addr];
|
||||||
}
|
}
|
||||||
|
|
||||||
void CTileGen::WriteRAM(unsigned addr, UINT32 data)
|
void CTileGen::WriteRAM32(unsigned addr, UINT32 data)
|
||||||
{
|
{
|
||||||
if (g_Config.gpuMultiThreaded)
|
if (g_Config.gpuMultiThreaded)
|
||||||
MARK_DIRTY(vramDirty, addr);
|
MARK_DIRTY(vramDirty, addr);
|
||||||
|
|
@ -296,6 +296,38 @@ void CTileGen::WriteRAM(unsigned addr, UINT32 data)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
//TODO: 8- and 16-bit handlers have not been thoroughly tested
|
||||||
|
uint8_t CTileGen::ReadRAM8(unsigned addr)
|
||||||
|
{
|
||||||
|
return vram[addr];
|
||||||
|
}
|
||||||
|
|
||||||
|
void CTileGen::WriteRAM8(unsigned addr, uint8_t data)
|
||||||
|
{
|
||||||
|
uint32_t tmp = ReadRAM32(addr & ~3);
|
||||||
|
size_t shift = (addr & 3) * 8;
|
||||||
|
uint32_t mask = 0xff << shift;
|
||||||
|
tmp &= ~mask;
|
||||||
|
tmp |= uint32_t(data) << shift;
|
||||||
|
WriteRAM32(addr & ~3, tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Star Wars Trilogy uses this
|
||||||
|
uint16_t CTileGen::ReadRAM16(unsigned addr)
|
||||||
|
{
|
||||||
|
return *((uint16_t *) &vram[addr]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void CTileGen::WriteRAM16(unsigned addr, uint16_t data)
|
||||||
|
{
|
||||||
|
uint32_t tmp = ReadRAM32(addr & ~1);
|
||||||
|
size_t shift = (addr & 1) * 16;
|
||||||
|
uint32_t mask = 0xffff << shift;
|
||||||
|
tmp &= ~mask;
|
||||||
|
tmp |= uint32_t(data) << shift;
|
||||||
|
WriteRAM32(addr & ~1, tmp);
|
||||||
|
}
|
||||||
|
|
||||||
void CTileGen::InitPalette(void)
|
void CTileGen::InitPalette(void)
|
||||||
{
|
{
|
||||||
for (int i = 0; i < 0x20000/4; i++)
|
for (int i = 0; i < 0x20000/4; i++)
|
||||||
|
|
|
||||||
|
|
@ -137,11 +137,13 @@ public:
|
||||||
void EndFrame(void);
|
void EndFrame(void);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* ReadRAM(addr):
|
* ReadRAM8(addr):
|
||||||
|
* ReadRAM16(addr):
|
||||||
|
* ReadRAM32(addr):
|
||||||
*
|
*
|
||||||
* Reads the tile generator's little endian RAM (the word is returned with
|
* Reads the tile generator's little endian RAM (the word is returned with
|
||||||
* the MSB read from addr+3). If a big endian device is reading (PowerPC),
|
* the MSB read from addr+3). If a big endian device is reading (PowerPC),
|
||||||
* the result must be manually flipped.
|
* the result must be manually adjusted.
|
||||||
*
|
*
|
||||||
* Parameters:
|
* Parameters:
|
||||||
* addr Address in tile generator RAM. Caller must ensure it is
|
* addr Address in tile generator RAM. Caller must ensure it is
|
||||||
|
|
@ -149,16 +151,20 @@ public:
|
||||||
* function does not.
|
* function does not.
|
||||||
*
|
*
|
||||||
* Returns:
|
* Returns:
|
||||||
* A 32-bit word read as little endian from the RAM address.
|
* Data from the RAM address.
|
||||||
*/
|
*/
|
||||||
UINT32 ReadRAM(unsigned addr);
|
uint8_t ReadRAM8(unsigned addr);
|
||||||
|
uint16_t ReadRAM16(unsigned addr);
|
||||||
|
uint32_t ReadRAM32(unsigned addr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* WriteRAM(addr, data):
|
* WriteRAM8(addr, data):
|
||||||
|
* WriteRAM16(addr, data):
|
||||||
|
* WriteRAM32(addr, data):
|
||||||
*
|
*
|
||||||
* Writes to the tile generator's little endian RAM (the word's MSB is
|
* Writes to the tile generator's little endian RAM (the word's MSB is
|
||||||
* written to addr+3). If a big endian device is writing, the word must be
|
* written to addr+3). If a big endian device is writing, the address and
|
||||||
* flipped manually before passing it to this function.
|
* data must be adjusted manually before passing it to this function.
|
||||||
*
|
*
|
||||||
* Parameters:
|
* Parameters:
|
||||||
* addr Address in tile generator RAM. Caller must ensure it is
|
* addr Address in tile generator RAM. Caller must ensure it is
|
||||||
|
|
@ -166,7 +172,9 @@ public:
|
||||||
* function does not.
|
* function does not.
|
||||||
* data The data to write.
|
* data The data to write.
|
||||||
*/
|
*/
|
||||||
void WriteRAM(unsigned addr, UINT32 data);
|
void WriteRAM8(unsigned addr, uint8_t data);
|
||||||
|
void WriteRAM16(unsigned addr, uint16_t data);
|
||||||
|
void WriteRAM32(unsigned addr, uint32_t data);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* ReadRegister(reg):
|
* ReadRegister(reg):
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue