mirror of
https://github.com/RetroDECK/Supermodel.git
synced 2024-11-25 15:15:40 +00:00
Changes to allow debugging of Z80 core:
- added methods to attach/detach debugger. - added hooks into CZ80Debug to allow debugger to control execution. - added methods to allow reading/writing of Z80 registers.
This commit is contained in:
Nik Henson
parent
041e6659b3
commit
65536fd0fe
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@ -30,8 +30,8 @@
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*/
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#include <cstdio> // for NULL
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#include "Z80.h" // must include this first to define CZ80
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#include "Supermodel.h"
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#include "Z80.h" // must include this first to define CZ80
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/******************************************************************************
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@ -228,16 +228,6 @@ static const unsigned char cycleTables[5][256] = {
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pc += 2; \
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}
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// Save local copies of Z80 registers back to context
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#define SAVE_TO_CONTEXT() \
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af[af_sel] = AF; \
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regs[regs_sel].bc = BC; \
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regs[regs_sel].de = DE; \
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regs[regs_sel].hl = HL; \
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ix = IX; \
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iy = IY; \
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sp = SP
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/*******************************************************************************
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Functions
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@ -245,6 +235,16 @@ static const unsigned char cycleTables[5][256] = {
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int CZ80::Run(int numCycles)
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{
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#ifdef SUPERMODEL_DEBUGGER
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// If debugging enabled, don't optimize access to registers as they need to be accesible to debugger during execution
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#define AF af[af_sel]
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#define BC regs[regs_sel].bc
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#define DE regs[regs_sel].de
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#define HL regs[regs_sel].hl
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#define SP sp
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#define IX ix
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#define IY iy
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#else
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// Optimization: copy registers into native word-sized local variables
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unsigned int AF = af[af_sel];
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unsigned int BC = regs[regs_sel].bc;
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@ -253,13 +253,31 @@ int CZ80::Run(int numCycles)
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unsigned int SP = sp;
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unsigned int IX = ix;
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unsigned int IY = iy;
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#endif
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unsigned int temp, acu, sum, cbits;
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unsigned int op, adr;
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int cycles = numCycles;
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#ifdef SUPERMODEL_DEBUGGER
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if (Debug != NULL)
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{
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Debug->CPUActive();
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lastCycles += numCycles;
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}
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#endif // SUPERMODEL_DEBUGGER
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while (cycles > 0)
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{
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op = GetBYTE_pp(pc);
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#ifdef SUPERMODEL_DEBUGGER
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if (Debug != NULL)
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{
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while (Debug->CPUExecute(pc - 1, op, lastCycles - cycles))
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op = GetBYTE_pp(pc);
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lastCycles = cycles;
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}
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#endif // SUPERMODEL_DEBUGGER
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switch(op) {
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case 0x00: /* NOP */
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cycles -= cycleTables[0][0x00];
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@ -3617,6 +3635,12 @@ int CZ80::Run(int numCycles)
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* - Clear IFF1 (disable interrupts)
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* - Un-halt CPU (if in HALT state)
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*/
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#ifdef SUPERMODEL_DEBUGGER
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if (Debug != NULL)
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Debug->CPUException(Z80_EX_NMI);
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#endif // SUPERMODEL_DEBUGGER
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PUSH(pc);
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pc = 0x0066;
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iff = (iff&~2) | ((iff&1)<<1);
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@ -3658,6 +3682,11 @@ int CZ80::Run(int numCycles)
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{
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v = INTCallback(this);
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#ifdef SUPERMODEL_DEBUGGER
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if (Debug != NULL)
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Debug->CPUException(v);
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#endif // SUPERMODEL_DEBUGGER
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switch (v)
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{
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case Z80_INT_RST_00: v = 0x0000; break;
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@ -3687,6 +3716,12 @@ int CZ80::Run(int numCycles)
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*
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* Vector is 0x0038.
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*/
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#ifdef SUPERMODEL_DEBUGGER
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if (Debug != NULL)
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Debug->CPUException(Z80_IM1_IRQ);
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#endif // SUPERMODEL_DEBUGGER
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PUSH(pc);
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pc = 0x0038;
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iff = 0;
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@ -3703,6 +3738,12 @@ int CZ80::Run(int numCycles)
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* and 8 bits read from the bus (with bit 0 cleared). The final
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* 16-bit vector is read from this address.
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*/
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#ifdef SUPERMODEL_DEBUGGER
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if (Debug != NULL)
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Debug->CPUException(Z80_IM2_VECTOR);
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#endif // SUPERMODEL_DEBUGGER
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if (NULL != INTCallback)
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{
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v = INTCallback(this);
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@ -3726,7 +3767,22 @@ int CZ80::Run(int numCycles)
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// write registers back to context
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HALTExit:
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SAVE_TO_CONTEXT();
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#ifdef SUPERMODEL_DEBUGGER
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if (Debug != NULL)
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{
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Debug->CPUInactive();
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lastCycles = lastCycles - cycles;
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}
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#else
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// Save local copies of Z80 registers back to context
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af[af_sel] = AF;
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regs[regs_sel].bc = BC;
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regs[regs_sel].de = DE;
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regs[regs_sel].hl = HL;
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ix = IX;
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iy = IY;
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sp = SP;
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#endif // SUPERMODEL_DEBUGGER
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// Return number of cycles actually executed
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return numCycles - cycles;
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@ -3747,6 +3803,90 @@ UINT16 CZ80::GetPC(void)
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return pc;
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}
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#ifdef SUPERMODEL_DEBUGGER
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UINT8 CZ80::GetReg8(unsigned reg8)
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{
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switch (reg8)
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{
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case Z80_REG8_IFF: return iff;
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case Z80_REG8_IM: return im;
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case Z80_REG8_I: return ir>>8;
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case Z80_REG8_R: return ir&0xFF;
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case Z80_REG8_A: return af[0]>>8;
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case Z80_REG8_F: return af[0]&0xFF;
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case Z80_REG8_B: return regs[0].bc>>8;
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case Z80_REG8_C: return regs[0].bc&0xFF;
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case Z80_REG8_D: return regs[0].de>>8;
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case Z80_REG8_E: return regs[0].de&0xFF;
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case Z80_REG8_H: return regs[0].hl>>8;
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case Z80_REG8_L: return regs[0].hl&0xFF;
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default: return 0;
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}
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}
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bool CZ80::SetReg8(unsigned reg8, UINT8 value)
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{
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switch (reg8)
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{
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case Z80_REG8_IFF: iff = value; return true;
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case Z80_REG8_IM: im = value; return true;
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case Z80_REG8_I: ir |= value<<8; return true;
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case Z80_REG8_R: ir |= value; return true;
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case Z80_REG8_A: af[0] |= value<<8; return true;
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case Z80_REG8_F: af[0] |= value; return true;
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case Z80_REG8_B: regs[0].bc |= value<<8; return true;
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case Z80_REG8_C: regs[0].bc |= value; return true;
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case Z80_REG8_D: regs[0].de |= value<<8; return true;
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case Z80_REG8_E: regs[0].de |= value; return true;
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case Z80_REG8_H: regs[0].hl |= value<<8; return true;
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case Z80_REG8_L: regs[0].hl |= value; return true;
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default: return false;
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}
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}
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UINT16 CZ80::GetReg16(unsigned reg16)
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{
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switch (reg16)
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{
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case Z80_REG16_SP: return sp;
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case Z80_REG16_PC: return pc;
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case Z80_REG16_IR: return ir;
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case Z80_REG16_AF: return af[0];
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case Z80_REG16_BC: return regs[0].bc;
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case Z80_REG16_DE: return regs[0].de;
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case Z80_REG16_HL: return regs[0].hl;
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case Z80_REG16_IX: return ix;
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case Z80_REG16_IY: return iy;
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case Z80_REG16_AF_: return af[1];
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case Z80_REG16_BC_: return regs[1].bc;
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case Z80_REG16_DE_: return regs[1].de;
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case Z80_REG16_HL_: return regs[1].hl;
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default: return 0;
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}
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}
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bool CZ80::SetReg16(unsigned reg16, UINT16 value)
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{
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switch (reg16)
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{
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case Z80_REG16_SP: sp = value; return true;
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case Z80_REG16_PC: pc = value; return true;
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case Z80_REG16_IR: ir = value; return true;
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case Z80_REG16_AF: af[0] = value; return true;
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case Z80_REG16_BC: regs[0].bc = value; return true;
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case Z80_REG16_DE: regs[0].de = value; return true;
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case Z80_REG16_HL: regs[0].hl = value; return true;
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case Z80_REG16_IX: ix = value; return true;
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case Z80_REG16_IY: iy = value; return true;
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case Z80_REG16_AF_: af[1] = value; return true;
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case Z80_REG16_BC_: regs[1].bc = value; return true;
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case Z80_REG16_DE_: regs[1].de = value; return true;
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case Z80_REG16_HL_: regs[1].hl = value; return true;
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default: return false;
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}
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}
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#endif // SUPERMODEL_DEBUGGER
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void CZ80::Reset(void)
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{
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pc = 0x0000;
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@ -3770,6 +3910,10 @@ void CZ80::Reset(void)
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intLine = false;
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nmiTrigger = false;
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#ifdef SUPERMODEL_DEBUGGER
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lastCycles = 0;
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#endif // SUPERMODEL_DEBUGGER
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}
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void CZ80::SaveState(CBlockFile *StateFile, const char *name)
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@ -3832,14 +3976,41 @@ void CZ80::Init(CBus *BusPtr, int (*INTF)(CZ80 *Z80))
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INTCallback = INTF;
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}
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#ifdef SUPERMODEL_DEBUGGER
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void CZ80::AttachDebugger(Debugger::CZ80Debug *DebugPtr)
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{
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if (Debug != NULL)
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DetachDebugger();
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Debug = DebugPtr;
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Bus = Debug->AttachBus(Bus);
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}
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void CZ80::DetachDebugger()
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{
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if (Debug == NULL)
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return;
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Bus = Debug->DetachBus();
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Debug = NULL;
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}
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#endif //SUPERMODEL_DEBUGGER
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CZ80::CZ80(void)
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{
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INTCallback = NULL; // so we can later check to see if one has been installed
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Bus = NULL;
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#ifdef SUPERMODEL_DEBUGGER
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Debug = NULL;
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#endif //SUPERMODEL_DEBUGGER
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}
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CZ80::~CZ80(void)
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{
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INTCallback = NULL;
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Bus = NULL;
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#ifdef SUPERMODEL_DEBUGGER
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Debug = NULL;
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#endif //SUPERMODEL_DEBUGGER
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}
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@ -64,6 +64,44 @@
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#define Z80_INT_RST_30 0xF7 // RST 0x30
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#define Z80_INT_RST_38 0xFF // RST 0x38
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#ifdef SUPERMODEL_DEBUGGER
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// Extra interrupt types
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#define Z80_EX_NMI 0
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#define Z80_IM1_IRQ 1
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#define Z80_IM2_VECTOR 2
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// 8-bit registers
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#define Z80_REG8_IFF 0
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#define Z80_REG8_IM 1
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#define Z80_REG8_I 2
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#define Z80_REG8_R 3
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#define Z80_REG8_A 4
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#define Z80_REG8_F 5
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#define Z80_REG8_B 6
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#define Z80_REG8_C 7
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#define Z80_REG8_D 8
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#define Z80_REG8_E 9
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#define Z80_REG8_H 10
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#define Z80_REG8_L 11
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// 16-bit registers
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#define Z80_REG16_SP 0
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#define Z80_REG16_PC 1
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#define Z80_REG16_IR 2
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#define Z80_REG16_AF 3
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#define Z80_REG16_BC 4
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#define Z80_REG16_DE 5
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#define Z80_REG16_HL 6
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#define Z80_REG16_IX 7
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#define Z80_REG16_IY 8
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#define Z80_REG16_AF_ 9
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#define Z80_REG16_BC_ 10
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#define Z80_REG16_DE_ 11
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#define Z80_REG16_HL_ 12
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class Debugger::CZ80Debug;
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#endif // SUPERMODEL_DEBUGGER
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/*
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* CZ80:
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*
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@ -103,8 +141,8 @@ public:
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* callbacks to clear interrupts.
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*
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* Parameters:
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* state If true, this is equivalent to /INT being asserted on the
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* Z80 (INT line low, which triggers an interrupt). If false,
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* state If TRUE, this is equivalent to /INT being asserted on the
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* Z80 (INT line low, which triggers an interrupt). If FALSE,
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* this deasserts /INT (INT line high, no interrupt pending).
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*/
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void SetINT(bool state);
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@ -119,6 +157,36 @@ public:
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*/
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UINT16 GetPC(void);
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#ifdef SUPERMODEL_DEBUGGER
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/*
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* GetReg8(state):
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*
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* Returns value of given 8-bit register.
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*/
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UINT8 GetReg8(unsigned reg8);
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/*
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* SetReg8(state):
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*
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* Sets value of given 8-bit register.
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*/
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bool SetReg8(unsigned reg8, UINT8 value);
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/*
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* GetReg16(state):
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*
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* Returns value of given 16-bit register.
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*/
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UINT16 GetReg16(unsigned reg16);
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/*
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* SetReg16(state):
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*
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* Sets value of given 16-bit register.
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*/
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bool SetReg16(unsigned reg16, UINT16 value);
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#endif // SUPERMODEL_DEBUGGER
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/*
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* Reset(void):
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*
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@ -161,7 +229,7 @@ public:
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*
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* An interrupt callback, which is called each time an interrupt occurs,
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* should also be supplied. The interrupt callback should explicitly clear
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* the INT status (using SetINT(false)) and then return the appropriate
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* the INT status (using SetINT(FALSE)) and then return the appropriate
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* vector depending on the interrupt mode that is used by the system.
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*
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* For mode 0, only Z80_INT_RST_* values are acceptable. For mode 1, the
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@ -183,6 +251,22 @@ public:
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*/
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void Init(CBus *BusPtr, int (*INTF)(CZ80 *Z80));
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#ifdef SUPERMODEL_DEBUGGER
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/*
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* AttachDebugger(DebugPtr):
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*
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* Attaches debugger to CPU.
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*/
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void AttachDebugger(Debugger::CZ80Debug *DebugPtr);
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/*
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* DetachDebugger():
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*
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* Detaches debugger from CPU.
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*/
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void DetachDebugger();
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#endif // SUPERMODEL_DEBUGGER
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/*
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* CZ80(void):
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* ~CZ80(void):
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@ -217,7 +301,12 @@ private:
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bool nmiTrigger;
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bool intLine;
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int (*INTCallback)(CZ80 *Z80);
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#ifdef SUPERMODEL_DEBUGGER
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int lastCycles;
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Debugger::CZ80Debug *Debug;
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#endif // SUPERMODEL_DEBUGGER
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};
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#endif // INCLUDED_Z80_H
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